Timing Information

Page 17

Configuration Devices for SRAM-Based LUT Devices

January 2012

Altera Corporation

Table 9 lists the timing parameters when using EPC1 and EPC1441 devices at 3.3 V.

Table 10 lists the timing parameters when using EPC1, EPC2, and EPC1441 devices at

5.0 V.

Table 9. Timing Parameters when Using EPC1 and EPC1441 Devices at 3.3 V

Symbol

Parameter

Min

Typ

Max

Units

POR delay (1)

——

200

ms

OE

high to DATA output enabled

—

—

80

ns

OE

high to first rising edge on DCLK

——

300

ns

Data

setup time before rising edge on DCLK

30

—

—

ns

Data

hold time after rising edge on DCLK

0—

—

ns

DCLK

to DATA out

—

—

30

ns

DCLK

to DATA enable/disable

—

—

30

ns

DCLK

frequency

2

4

10

MHz

DCLK

high time for the first device in the configuration chain

50

125

250

ns

DCLK

low time for the first device in the configuration chain

50

125

250

ns

DCLK

high time for subsequent devices

50

—

—

ns

DCLK

low time for subsequent devices

50

—

—

ns

DCLK

rising edge to nCASC

—

—

25

ns

nCS

to nCASC cascade delay

—

—

15

ns

OE

low pulse width (reset) to guarantee counter reset

100

—

—

ns

OE

low (reset) to DCLK disable delay

—

—

30

ns

OE

low (reset) to nCASC delay

—

—

30

ns

Note to Table 9:

(1) During initial power-up, a POR delay occurs to permit voltage levels to stabilize. Subsequent reconfigurations do not incur this delay.

Table 10. Timing Parameters when Using EPC1, EPC2, and EPC1441 Devices at 5.0 V (Part 1 of 2)

Symbol

Parameter

Min

Typ

Max

Units

POR delay (1)

——

200

ms

OE

high to DATA output enabled

—

—

50

ns

OE

high to first rising edge on DCLK

——

200

ns

Data

setup time before rising edge on DCLK

30

—

—

ns

Data

hold time after rising edge on DCLK

0—

—

ns

DCLK

to DATA out

—

—

20

ns

DCLK

to DATA enable/disable

—

—

20

ns

DCLK

frequency

6.7

10

16.7

MHz

DCLK

high time for the first device in the configuration chain

30

50

75

ns

DCLK

low time for the first device in the configuration chain

30

50

75

ns

DCLK

high time for subsequent devices

30

—

—

ns

DCLK

low time for subsequent devices

30

—

—

ns

DCLK

rising edge to nCASC

—

—

20

ns

nCS

to nCASC cascade delay

—

—

10

ns