PIC12F508ESLASHMS datasheet(17/110 Pages) MICROCHIP

17 / 110 page

DS41236E-page 17

PIC12F508/509/16F505

4.0

MEMORY ORGANIZATION

The PIC12F508/509/16F505 memories are organized

into program memory and data memory. For devices

with more than 512 bytes of program memory, a paging

scheme is used. Program memory pages are accessed

using one STATUS register bit. For the PIC12F509 and

PIC16F505, with data memory register files of more

than 32 registers, a banking scheme is used. Data

memory banks are accessed using the File Select

4.1

Program Memory Organization for

the PIC12F508/509

The PIC12F508 device has a 10-bit Program Counter

(PC) and PIC12F509 has a 11-bit Program Counter

(PC) capable of addressing a 2K x 12 program memory

space.

Only the first 512 x 12 (0000h-01FFh) for the

PIC12F508, and 1K x 12 (0000h-03FFh) for the

PIC12F509

are

physically

implemented

(see

Figure 4-1). Accessing a location above these

boundaries will cause a wrap-around within the first

512 x 12 space (PIC12F508) or 1K x 12 space

(PIC12F509). The effective Reset vector is a 0000h

(see Figure 4-1). Location 01FFh (PIC12F508) and

location 03FFh (PIC12F509) contain the internal

clock oscillator calibration value. This value should

never be overwritten.

FIGURE 4-1:

PROGRAM MEMORY MAP

AND STACK FOR THE

PIC12F508/509

CALL, RETLW

PC<11:0>

Stack Level 1

Stack Level 2

0000h

7FFh

01FFh

0200h

On-chip Program

Memory

Reset Vector(1)

Note

Address 0000h becomes the

effective Reset vector. Location

01FFh, 03FFh (PIC12F508,

PIC12F509) contains the MOVLW XX

internal oscillator calibration value.

512 Word

1024 Word

03FFh

0400h

On-chip Program

Memory

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