CLK13_7P datasheet(32/274 Pages) ALTERA

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Chapter 2: Logic Elements and Logic Array Blocks in the Cyclone III Device Family

LAB Control Signals

Cyclone III Device Handbook

December 2011

Altera Corporation

Volume 1

Figure 2–5 shows the direct link connection.

LAB Control Signals

Each LAB contains dedicated logic for driving control signals to its LEs. The control

signals include:

■

Two clocks

■

Two clock enables

■

Two asynchronous clears

■

One synchronous clear

■

One synchronous load

You can use up to eight control signals at a time. Register packing and synchronous

load cannot be used simultaneously.

Each LAB can have up to four non-global control signals. You can use additional LAB

control signals as long as they are global signals.

Synchronous clear and load signals are useful for implementing counters and other

functions. The synchronous clear and synchronous load signals are LAB-wide signals

that affect all registers in the LAB.

Each LAB can use two clocks and two clock enable signals. The clock and clock enable

signals of each LAB are linked. For example, any LE in a particular LAB using the

labclk1

signal also uses the labclkena1. If the LAB uses both the rising and falling

edges of a clock, it also uses both LAB-wide clock signals. Deasserting the clock

enable signal turns off the LAB-wide clock.

The LAB row clocks [5..0] and LAB local interconnect generate the LAB-wide

control signals. The MultiTrack interconnect inherent low skew allows clock and

control signal distribution in addition to data distribution.

Figure 2–5. Cyclone III Device Family Direct Link Connection

LAB

Direct link

interconnect

to right

Direct link interconnect from

right LAB, M9K memory

block, embedded multiplier,

PLL, or IOE output

Direct link interconnect from

left LAB, M9K memory

block, embedded multiplier,

PLL, or IOE output

Local

Interconnect

Direct link

interconnect

to left

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