công cụ tìm kiếm bảng dữ liệu linh kiện điện tử
  Vietnamese  ▼
ALLDATASHEET.VN

X  

Preview PDF HTML

EP3C40 bảng dữ liệu(PDF) 36 Page - Altera Corporation

tên linh kiện EP3C40
Giải thích chi tiết về linh kiện  This section provides a complete overview of all features relating to the Cyclone III device family
PDF  274 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
nhà sản xuất  ALTERA [Altera Corporation]
Trang chủ  http://www.altera.com
Logo ALTERA - Altera Corporation

EP3C40 bảng dữ liệu(HTML) 36 Page - Altera Corporation

Back Button EP3C40 Datasheet HTML 32Page - Altera Corporation EP3C40 Datasheet HTML 33Page - Altera Corporation EP3C40 Datasheet HTML 34Page - Altera Corporation EP3C40 Datasheet HTML 35Page - Altera Corporation EP3C40 Datasheet HTML 36Page - Altera Corporation EP3C40 Datasheet HTML 37Page - Altera Corporation EP3C40 Datasheet HTML 38Page - Altera Corporation EP3C40 Datasheet HTML 39Page - Altera Corporation EP3C40 Datasheet HTML 40Page - Altera Corporation Next Button
Zoom Inzoom in Zoom Outzoom out
 36 / 274 page
background image
3–2
Chapter 3: Memory Blocks in the Cyclone III Device Family
Overview
Cyclone III Device Handbook
December 2011
Altera Corporation
Volume 1
Table 3–1 lists the features supported by the M9K memory
f For information about the number of M9K memory blocks for the Cyclone III device
family, refer to the Cyclone III Device Family Overview chapter.
Table 3–1. Summary of M9K Memory Features
Feature
M9K Blocks
Configurations (depth × width)
8192 × 1
4096 × 2
2048 × 4
1024 × 8
1024 × 9
512 × 16
512 × 18
256 × 32
256 × 36
Parity bits
v
Byte enable
v
Packed mode
v
Address clock enable
v
Single-port mode
v
Simple dual-port mode
v
True dual-port mode
v
Embedded shift register mode (1)
v
ROM mode
v
FIFO buffer (1)
v
Simple dual-port mixed width support
v
True dual-port mixed width support (2)
v
Memory initialization file (.mif)
v
Mixed-clock mode
v
Power-up condition
Outputs cleared
Register asynchronous clears
Read address registers and output registers only
Latch asynchronous clears
Output latches only
Write or read operation triggering
Write and read: Rising clock edges
Same-port read-during-write
Outputs set to Old Data or New Data
Mixed-port read-during-write
Outputs set to Old Data or Don’t Care
Notes to Table 3–1:
(1) FIFO buffers and embedded shift registers that require external logic elements (LEs) for implementing control
logic.
(2) Width modes of ×32 and ×36 are not available.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


bảng dữ liệu tải về

Go To PDF Page


Link URL



Cho đến nay ALLDATASHEET có giúp ích cho doanh nghiệp của bạn hay không?  [ DONATE ] 

Alldatasheet là   |   Quảng cáo   |   Liên lạc với chúng tôi   |   Chính sách bảo mật   |   Liên kết đến bảng dữ liệu    |   Trao đổi link   |   Tìm kiếm theo nhà sản xuất
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com