PIC24FJ64GA108 datasheet(7/22 Pages) MICROCHIP

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 2008-2013 Microchip Technology Inc.

DS80368N-page 7

PIC24FJ256GA110 FAMILY

14. Module: Core (Instruction Set)

If an instruction producing a read-after-write stall

condition is executed inside a REPEAT loop, the

instruction will be executed fewer times than was

intended. For example, this loop:

repeat #0xf

inc [w1],[++w1]

will execute less than 15 times.

Work around

Avoid using REPEAT to repetitively execute

instructions that create a stall condition. Instead,

use a software loop using conditional branches.

The MPLAB® C Compiler will not generate

REPEAT loops that cause this erratum.

Affected Silicon Revisions

15. Module: Memory (Program Space

Visibility)

When accessing data in the PSV area of data

RAM, it is possible to generate a false address

error trap condition by reading data located pre-

cisely at the lower address boundary (8000h). If

data is read using an instruction with an

auto-decrement, the resulting RAM address will be

below the PSV boundary (i.e., at 7FFEh); this will

result in an address error trap.

This false address error can also occur if a 32-bit

MOV instruction is used to read the data at location

8000h.

Work around

Do not use the first location of a PSV page (address

8000h). The MPLAB® C Compiler (v3.11 or later)

supports the option “-merrata=psv_trap” to

prevent it from generating code that would cause this

erratum.

Affected Silicon Revisions

16. Module: ICSP™

The ICSP/ICD port pair, PGEC3/PGED3 (RB5/RB4),

cannot be used to read or program the device.

Work around

Use either PGEC2/PGED2 or PGEC1/PGED1.

Affected Silicon Revisions

17. Module: RTCC

Under certain circumstances, the value of the Alarm

Repeat Counter register (ALCFGRPT<7:0>) may

be unexpectedly decremented. This happens only

when a byte write to the upper byte of ALCFGRPT

is performed in the interval between a device

POR/BOR and the first edge from the RTCC clock

source.

Work around

Do not perform byte writes on ALCFGRPT,

particularly the upper byte.

Alternatively, wait until one period of the SOSC

has completed before performing byte writes to

ALCFGRPT.

Affected Silicon Revisions

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