H5TC2G63FFR-RDA datasheet(15/32 Pages) HYNIX

15 / 32 page

Rev. 1.1 / Apr. 2013

IDD2N

Precharge Standby Current

CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address,

Bank Address Inputs: partially toggling according to Table 5; Data IO: MID_LEVEL; DM: stable at 0;

Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable

at 0; Pattern Details: see Table 5.

IDD2NT

Precharge Standby ODT Current

CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address,

Bank Address Inputs: partially toggling according to Table 6; Data IO: MID_LEVEL; DM: stable at 0;

Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: tog-

gling according to Table 6; Pattern Details: see Table 6.

IDD2P0

Precharge Power-Down Current Slow Exit

CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address,

Bank Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed;

Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Precharge Power Down

Mode: Slow Exitc)

IDD2P1

Precharge Power-Down Current Fast Exit

CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address,

Bank Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed;

Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Precharge Power Down

Mode: Fast Exitc)

IDD2Q

Precharge Quiet Standby Current

CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address,

Bank Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed;

Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0

IDD3N

Active Standby Current

CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address,

Bank Address Inputs: partially toggling according to Table 5; Data IO: MID_LEVEL; DM: stable at 0;

Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable

at 0; Pattern Details: see Table 5.

Symbol

Description

H5TC2G63FFR-RDA bảng dữ liệu(PDF) 15 Page - Hynix Semiconductor