MCR03EZPFX1002 datasheet(14/36 Pages) IRF

14 / 36 page

IR3837MPbF

Rev 1.31

Fig. 5b. Pre-Bias startup pulses

Fig. 5a. Pre-Bias startup

Fig. 4b. Recommended startup for sequencing

operation (ratiometric or simultaneous)

Fig. 4c. Recommended startup for memory

tracking operation (Vtt-DDR)

Vref

This pin reflects the internal reference voltage

which is used by the error amplifier to set the

output voltage. In most operating conditions this

pin is only connected to an external bypass

capacitor and it is left floating. In tracking mode

this pin should be connected to an external

voltage greater than 1.5V and less than 7V. For

margining applications, an external voltage

source is connected to Vref pin and overrides

the internal reference voltage. The external

voltage source should have a low internal

resistance (<100Ω) and be able to source and

sink more than 25µA.

Pre-Bias Startup

IR3837 is able to start up into pre-charged

output,

which

prevents

oscillation

and

disturbances of the output voltage.

The output starts in asynchronous fashion and

keeps the synchronous MOSFET (sync FET)

off until the first gate signal for control MOSFET

(control FET) is generated. Figure 5a shows a

typical Pre-Bias condition at start up. The sync

FET always starts with a narrow pulse width

and gradually increases its duty cycle with a

step of 25%, 50%, 75% and 100% until it

reaches the steady state value. The number of

these startup pulses for the sync FET is

internally programmed. Figure 5b shows a

series of 32, 16, 8 startup pulses.

Fig. 4a. Recommended startup for

Normal operation

Pvin (12V)

Vcc (5.2V)

Enable> 1. 2 V

Pvin (12V)

Vcc (5.2V)

Enable > 1. 2 V

Vcc > Vref > 1.5V

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