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MCR03EZPFX1002 bảng dữ liệu(PDF) 26 Page - International Rectifier

tên linh kiện MCR03EZPFX1002
Giải thích chi tiết về linh kiện  HIGHLY INTEGRATED 14A SINGLE-INPUT VOLTAGE, SYNCHRONOUS BUCK REGULATOR
PDF  36 Pages
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nhà sản xuất  IRF [International Rectifier]
Trang chủ  http://www.irf.com
Logo IRF - International Rectifier

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26
IR3837MPbF
Rev 1.31
Select crossover frequency F
0=100 kHz
Since F
LC<F0<Fs/2<FESR, Type III is selected to
place the pole and zeros.
Detailed calculation of compensation Type III :
kΩ
2
:
Select
kΩ
2.01
-
kΩ
4.02
:
Select
kΩ
3.98
-
2
1
Ω
127
:
Select
Ω
127.5
;
2
1
and
Calculate
pF
120
:
Select
pF
132
2
1
nF
7
4
:
Select
nF,
49
4
;
*
2
1
k
4.02
Select
kΩ
98
3
2
:
and
,
Calculate
nF
2.2
C
:
Select
kHz
300
*
0.5
and
kHz
8.82
5
0
Select
kHz
567.1
1
1
kHz
17.63
1
1
70
Margin
Phase
Desired
9
9
8
9
8
8
10
2
7
8
10
10
2
7
10
9
8
10
3
3
3
3
3
4
4
3
1
4
3
3
7
3
4
3
3
7
3
2
1
2
2
o
R
R
;
R
*
V
V
V
R
R
,
R
;
R
F
*
C
*
π
R
R
,
R
F
*
C
*
π
R
:
R
R
,
R
C
,
C
;
R
*
F
*
π
C
.
C
.
C
R
*
F
π
C
R
:
.
R
;
V
*
C
V
*
C
*
L
*
F
*
π
R
C
C
R
F
F
F
*
.
F
:
sin
sin
F
F
sin
sin
F
F
ref
o
ref
Z
P
P
Z
in
osc
o
o
o
s
P
Z
Z
o
P
o
Z
Programming the Current-Limit
The Current-Limit threshold can be set by
connecting a resistor (R
OCSet) from the SW pin
to the OCSet pin. The resistor can be calculated
by using equation (4). This resistor (R
OCSet)must
be placed close to the IC.
The
R
DS(on)
has
a
positive
temperature
coefficient and it should be considered for the
worst case operation (40% increase due to
temperature has been considered in below).
The optional filter capacitor from OCSet pin to
PGnd has not been used for this design.
Setting the Power Good Threshold
In this design IR3837 is used in normal (non-
tracking, non-sequencing) mode, therefore the
PGood thresholds are internally set at 85% and
115% of Vref. At startup as soon as the internal
soft start signal reaches 2V (Figure 11), and
assuming Fb voltage follows Vref, the PGood is
asserted. As long as the voltage at the Fb pin is
between the thresholds (mentioned above),
Enable is high, and no fault happens, the PGood
remains high.
The PGood is an open drain output. Hence, it is
necessary to use a pull up resistor, R
PG, from
PGood pin to Vcc.
The value of the pull-up
resistor must be chosen such as to limit the
current flowing into the PGood pin to less than
5mA when the output voltage is not in regulation.
A typical value used is 10kΩ.
Vref Bypass Capacitor
A bypass capacitor of about 0.1uF is required to
be placed between Vref and Gnd pins. This
capacitor should be placed as close as possible
to Vref pin.
kΩ
23
5
R
Select
kΩ
28
5
R
kHz)
600
(at
μA
29.54
I
)
current
output
nominal
over
(50%
A
21
1.5
*
A
14
mΩ
7.42
1.4
*
mΩ
3
5
OCSet
OCSet
OCSet
.
.
F
I
I
.
R
s
)
LIM
(
o
SET
)
on
(
DS
(33)
...
..........
..........
R
I
R
I
I
)
on
(
DS
OCSet
OCSet
)
critical
(
L
SET



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