STM8AF6148 datasheet(40/89 Pages) STMICROELECTRONICS

40 / 89 page

Interrupt table

STM8AF61xx, STM8AF62xx

40/89

Doc ID 14952 Rev 6

Interrupt table

Table 16.

STM8A interrupt table

Priority

Source

block

Description

Interrupt vector

address

Wakeup

from Halt

Comments

—

Reset

0x00 6000

Yes

Reset vector in ROM

—

TRAP

SW interrupt

0x00 8004

—

TLI

External top level interrupt

0x00 8008

—

AWU

Auto-wakeup from Halt

0x00 800C

Yes

—

Clock

controller

Main clock controller

0x00 8010

—

MISC

Ext interrupt E0

0x00 8014

Yes

Port A interrupts

MISC

Ext interrupt E1

0x00 8018

Yes

Port B interrupts

MISC

Ext interrupt E2

0x00 801C

Yes

Port C interrupts

MISC

Ext interrupt E3

0x00 8020

Yes

Port D interrupts

MISC

Ext interrupt E4

0x00 8024

Yes

Port E interrupts

Reserved(1)

All reserved and unused interrupts must be initialized with ‘IRET’ for robust programming.

——

—

Reserved(1)

——

—

SPI

End of transfer

0x00 8030

Yes

—

Timer 1

Update/overflow/

trigger/break

0x00 8034

—

Timer 1

Capture/compare

0x00 8038

—

Timer 2

Update/overflow

0x00 803C

—

Timer 2

Capture/compare

0x00 8040

—

Timer 3

Update/overflow

0x00 8044

—

Timer 3

Capture/compare

0x00 8048

—

Reserved(1)

——

—

Reserved(1)

——

—

I2C

I2C interrupts

0x00 8054

Yes

—

LINUART

Tx complete/error

0x00 8058

—

LINUART

Receive data full reg.

0x00 805C

—

ADC

End of conversion

0x00 8060

—

Timer 4

Update/overflow

0x00 8064

—

EEPROM

End of Programming/

Write in not allowed area

0x00 8068

—

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