DSPIC33FJMC202ESS datasheet(71/330 Pages) MICROCHIP

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DS70283K-page 71

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304

7.0

INTERRUPT CONTROLLER

The

dsPIC33FJ32MC202/204

and

dsPIC33FJ16MC304 interrupt controller reduces the

numerous peripheral interrupt request signals to a

single

interrupt

request

signal

the

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304

CPU. It has the following features:

• Up to 8 processor exceptions and software traps

• 7 user-selectable priority levels

• Interrupt Vector Table (IVT) with up to 118 vectors

• A unique vector for each interrupt or exception

source

• Fixed priority within a specified user priority level

• Alternate Interrupt Vector Table (AIVT) for debug

support

• Fixed interrupt entry and return latencies

7.1

Interrupt Vector Table

The Interrupt Vector Table (IVT) is shown in Figure 7-1.

The IVT resides in program memory, starting at location

000004h. The IVT contains 126 vectors consisting of

8 nonmaskable trap vectors plus up to 118 sources of

interrupt. In general, each interrupt source has its own

vector. Each interrupt vector contains a 24-bit-wide

address. The value programmed into each interrupt

vector location is the starting address of the associated

Interrupt Service Routine (ISR).

Interrupt vectors are prioritized in terms of their natural

priority. This priority is linked to their position in the

vector table. Lower addresses generally have a higher

natural priority. For example, the interrupt associated

with vector 0 will take priority over interrupts at any

other vector address.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304

devices implement up to 26 unique interrupts and 4

nonmaskable traps. These are summarized in

Table 7-1 and Table 7-2.

7.1.1

ALTERNATE INTERRUPT VECTOR

TABLE

The Alternate Interrupt Vector Table (AIVT) is located

after the IVT, as shown in Figure 7-1. Access to the

AIVT is provided by the ALTIVT control bit

(INTCON2<15>). If the ALTIVT bit is set, all interrupt

and exception processes use the alternate vectors

instead of the default vectors. The alternate vectors are

organized in the same manner as the default vectors.

The AIVT supports debugging by providing a means to

switch between an application and a support

environment without requiring the interrupt vectors to

be reprogrammed. This feature also enables switching

between applications for evaluation of different

software algorithms at run time. If the AIVT is not

needed, the AIVT should be programmed with the

same addresses used in the IVT.

7.2

Reset Sequence

A device Reset is not a true exception because the

interrupt controller is not involved in the Reset process.

The

dsPIC33FJ32MC202/204

and

dsPIC33FJ16MC304 device clears its registers in

response to a Reset, which forces the PC to zero. The

digital signal controller then begins program execution

at location 0x000000. A GOTO instruction at the Reset

address can redirect program execution to the

appropriate start-up routine.

Note 1: This data sheet summarizes the features

of the dsPIC33FJ32MC202/204 and

dsPIC33FJ16MC304 devices. It is not

intended to be a comprehensive refer-

ence source. To complement the infor-

mation in this data sheet, refer to Section

32. “Interrupts (Part III)” (DS70214) of

the “dsPIC33F/PIC24H Family Reference

Manual”, which is available from the

Microchip web site (www.microchip.com).

2: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

Note:

Any unimplemented or unused vector

locations in the IVT and AIVT should be

programmed with the address of a default

interrupt handler routine that contains a

RESET instruction.

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