DSPIC33FJ12MC201TESS datasheet(69/304 Pages) MICROCHIP

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DS70265E-page 69

dsPIC33FJ12MC201/202

6.4

External Reset (EXTR)

The external Reset is generated by driving the MCLR

pin low. The MCLR pin is a Schmitt trigger input with an

additional glitch filter. Reset pulses that are longer than

the minimum pulse width will generate a Reset. Refer

to Section 24.0 “Electrical Characteristics” for

minimum pulse width specifications. The External

Reset (MCLR) Pin (EXTR) bit in the Reset Control

(RCON) register is set to indicate the MCLR Reset.

6.4.1

EXTERNAL SUPERVISORY CIRCUIT

Many systems have external supervisory circuits that

generate Reset signals to Reset multiple devices in the

system. This external Reset signal can be directly con-

nected to the MCLR pin to Reset the device when the

rest of system is Reset.

6.4.2

INTERNAL SUPERVISORY CIRCUIT

When using the internal power supervisory circuit to

Reset the device, the external Reset pin (MCLR)

should be tied directly or resistively to VDD. In this case,

the MCLR pin will not be used to generate a Reset. The

external Reset pin (MCLR) does not have an internal

pull-up and must not be left unconnected.

6.5

Software RESET Instruction (SWR)

Whenever the RESET instruction is executed, the

device will assert SYSRST, placing the device in a

special Reset state. This Reset state will not re-

initialize the clock. The clock source in effect prior to the

RESET

instruction will remain. SYSRST is released at

the next instruction cycle, and the Reset vector fetch

will commence.

The Software Reset (Instruction) Flag (SWR) bit in the

Reset Control (RCON<6>) register is set to indicate

the software Reset.

6.6

Watchdog Time-out Reset (WDTO)

Whenever a Watchdog Time-out occurs, the device

will asynchronously assert SYSRST. The clock source

will remain unchanged. A WDT time-out during Sleep

or Idle mode will wake-up the processor, but will not

reset the processor.

The Watchdog Timer Time-out Flag (WDTO) bit in the

Reset Control (RCON<4>) register is set to indicate

the

Watchdog

Reset.

Refer

Section 21.4

“Watchdog Timer (WDT)”

for more information on

Watchdog Reset.

6.7

Trap Conflict Reset

If a lower-priority hard trap occurs while a higher-prior-

ity trap is being processed, a hard trap conflict Reset

occurs. The hard traps include exceptions of priority

level 13 through level 15, inclusive. The address error

(level 13) and oscillator error (level 14) traps fall into

this category.

The Trap Reset Flag (TRAPR) bit in the Reset Control

(RCON<15>) register is set to indicate the Trap Conflict

Reset. Refer to Section 7.0 “Interrupt Controller” for

more information on trap conflict Resets.

6.8

Configuration Mismatch Reset

To maintain the integrity of the peripheral pin select

control registers, they are constantly monitored with

shadow registers in hardware. If an unexpected

change in any of the registers occur (such as cell dis-

turbances caused by ESD or other external events), a

configuration mismatch Reset occurs.

The Configuration Mismatch Flag (CM) bit in the

Reset Control (RCON<9>) register is set to indicate

the

configuration

mismatch

Reset.

Refer

Section 10.0 “I/O Ports”

for more information on the

configuration mismatch Reset.

6.9

Illegal Condition Device Reset

An illegal condition device Reset occurs due to the

following sources:

• Illegal Opcode Reset

• Uninitialized W Register Reset

• Security Reset

The Illegal Opcode or Uninitialized W Access Reset

Flag (IOPUWR) bit in the Reset Control (RCON<14>)

Reset.

Note:

The configuration mismatch feature and

associated Reset flag is not available on

all devices.

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