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DSPIC33FJ12MC201TESS bảng dữ liệu(PDF) 20 Page - Microchip Technology |
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DSPIC33FJ12MC201TESS bảng dữ liệu(HTML) 20 Page - Microchip Technology |
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20 / 304 page ![]() dsPIC33FJ12MC201/202 DS70265E-page 20 © 2007-2011 Microchip Technology Inc. The dsPIC33FJ12MC201/202 supports 16/16 and 32/ 16 divide operations, both fractional and integer. All divide instructions are iterative operations. They must be executed within a REPEAT loop, resulting in a total execution time of 19 instruction cycles. The divide operation can be interrupted during any of those 19 cycles without loss of data. A 40-bit barrel shifter is used to perform up to a 16-bit left or right shift in a single cycle. The barrel shifter can be used by both MCU and DSP instructions. FIGURE 3-1: dsPIC33FJ12MC201/202 CPU CORE BLOCK DIAGRAM Instruction Decode and Control PCH PCL Program Counter 16-bit ALU 24 23 Instruction Reg PCU 16 x 16 W Register Array ROM Latch EA MUX Interrupt Controller Stack Control Logic Loop Control Logic Data Latch Address Latch Control Signals to Various Blocks 16 16 16 To Peripheral Modules Data Latch Address Latch 16 X RAM Y RAM Address Generator Units 16 Y Data Bus X Data Bus DSP Engine Divide Support 16 16 23 23 16 8 PSV and Table Data Access Control Block 16 16 16 16 Program Memory Data Latch Address Latch |
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