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DSPIC33FJ12MC201TESS bảng dữ liệu(PDF) 298 Page - Microchip Technology |
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DSPIC33FJ12MC201TESS bảng dữ liệu(HTML) 298 Page - Microchip Technology |
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298 / 304 page  dsPIC33FJ12MC201/202 DS70265E-page 298 © 2007-2011 Microchip Technology Inc. Fundamental Modes Supported.................................. 49 MAC Instructions......................................................... 49 MCU Instructions ........................................................ 48 Move and Accumulator Instructions............................ 49 Other Instructions........................................................ 49 Instruction Set Overview ................................................................... 214 Summary................................................................... 211 Instruction-Based Power-Saving Modes ........................... 113 Idle ............................................................................ 114 Sleep......................................................................... 113 Internal RC Oscillator Use with WDT ........................................................... 209 Internet Address................................................................ 301 Interrupt Control and Status Registers................................ 75 IECx ............................................................................ 75 IFSx............................................................................. 75 INTCON1 .................................................................... 75 INTCON2 .................................................................... 75 IPCx ............................................................................ 75 Interrupt Setup Procedures ............................................... 101 Initialization ............................................................... 101 Interrupt Disable........................................................ 101 Interrupt Service Routine .......................................... 101 Trap Service Routine ................................................ 101 Interrupt Vector Table (IVT) ................................................ 71 Interrupts Coincident with Power Save Instructions.......... 114 J JTAG Boundary Scan Interface ........................................ 205 JTAG Interface .................................................................. 210 M Memory Organization.......................................................... 31 Microchip Internet Web Site .............................................. 301 Modulo Addressing ............................................................. 50 Applicability ................................................................. 51 Operation Example ..................................................... 50 Start and End Address................................................ 50 W Address Register Selection .................................... 50 Motor Control PWM........................................................... 155 Motor Control PWM Module 2-Output Register Map................................................ 41 4-Output Register Map................................................ 40 6-Output Register Map................................................ 40 MPLAB ASM30 Assembler, Linker, Librarian ................... 220 MPLAB Integrated Development Environment Software .. 219 MPLAB PM3 Device Programmer..................................... 222 MPLAB REAL ICE In-Circuit Emulator System................. 221 MPLINK Object Linker/MPLIB Object Librarian ................ 220 N NVM Module Register Map............................................................... 47 O Open-Drain Configuration ................................................. 120 Output Compare................................................................ 151 P Packaging ......................................................................... 271 Details ....................................................................... 273 Marking ............................................................. 271, 272 Peripheral Module Disable (PMD)..................................... 114 Pinout I/O Descriptions (table) ............................................ 11 PMD Module Register Map .............................................................. 47 PORTA Register Map .............................................................. 46 PORTB Register Map for dsPIC33FJ12MC201....................... 46 Register Map for dsPIC33FJ12MC202....................... 46 Power-on Reset (POR)....................................................... 68 Power-Saving Features .................................................... 113 Clock Frequency and Switching ............................... 113 Program Address Space..................................................... 31 Construction ............................................................... 53 Data Access from Program Memory Using Program Space Visibility ................................................... 56 Data Access from Program Memory Using Table Instruc- tions .................................................................... 55 Data Access from, Address Generation ..................... 54 Memory Map............................................................... 31 Table Read Instructions TBLRDH ............................................................. 55 TBLRDL.............................................................. 55 Visibility Operation ...................................................... 56 Program Memory Interrupt Vector........................................................... 32 Organization ............................................................... 32 Reset Vector............................................................... 32 PWM Time Base............................................................... 158 Q Quadrature Encoder Interface (QEI)................................. 169 Quadrature Encoder Interface (QEI) Module Register Map .............................................................. 41 R Reader Response............................................................. 302 Registers AD1CHS123 (ADC1 Input Channel 1, 2, 3 Select)... 201 ADxCHS0 (ADCx Input Channel 0 Select ................ 203 ADxCON1 (ADCx Control 1)..................................... 197 ADxCON2 (ADCx Control 2)..................................... 199 ADxCON3 (ADCx Control 3)..................................... 200 ADxCSSL (ADCx Input Scan Select Low) ................ 204 ADxPCFGL (ADCx Port Configuration Low)............. 204 CLKDIV (Clock Divisor) ............................................ 109 CORCON (Core Control) ...................................... 24, 76 DFLTxCON (QEI Control)......................................... 172 I2CxCON (I2Cx Control) ........................................... 181 I2CxMSK (I2Cx Slave Mode Address Mask) ............ 185 I2CxSTAT (I2Cx Status) ........................................... 183 IEC0 (Interrupt Enable Control 0) ............................... 85 IEC1 (Interrupt Enable Control 1) ............................... 87 IEC3 (Interrupt Enable Control 3) ............................... 88 IEC4 (Interrupt Enable Control 4) ............................... 89 IFS0 (Interrupt Flag Status 0) ..................................... 80 IFS1 (Interrupt Flag Status 1) ..................................... 82 IFS3 (Interrupt Flag Status 3) ..................................... 83 IFS4 (Interrupt Flag Status 4) ..................................... 84 INTCON1 (Interrupt Control 1).................................... 77 INTCON2 (Interrupt Control 2).................................... 79 INTTREG Interrupt Control and Status Register ...... 100 IPC0 (Interrupt Priority Control 0) ............................... 90 IPC1 (Interrupt Priority Control 1) ............................... 91 IPC14 (Interrupt Priority Control 14) ........................... 97 IPC15 (Interrupt Priority Control 15) ........................... 98 IPC16 (Interrupt Priority Control 16) ........................... 98 IPC18 (Interrupt Priority Control 18) ........................... 99 IPC2 (Interrupt Priority Control 2) ............................... 92 |
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