AD9914PCBZ datasheet(14/48 Pages) AD

14 / 48 page

AD9914

Data Sheet

Rev. C | Page 14 of 48

Figure 16. Absolute Phase Noise Curves of Normalized REF CLK Source to

DDS Output at 1396 MHz (SYSCLK = 3.5 GHz)

Figure 17. Residual Phase Noise Curves

Figure 18. Power Supply Current vs. SYSCLK

Figure 19. Absolute Phase Noise Curves of DDS Output Using Internal PLL at

2.5 GHz Operation

Figure 20. Residual PN vs. Absolute PN Measurement Curves at 1396 MHz

Figure 21. Residual Phase Noise vs. Normalized Absolute REF CLK Source

Phase Noise at 1396 MHz

100

10k

100k

10M

100M

FREQUENCY OFFSET (Hz)

–70

–90

–80

–100

–110

–120

–130

–140

–150

–160

–170

1396MHz

NORMALIZED

REF CLK SOURCE

–60

–90

–80

–70

–100

–110

–120

–130

–140

–150

–160

–170

–180

100

10k

100k

10M

100M

FREQUENCY OFFSET (Hz)

427MHz

1396MHz

696MHz

171MHz

0.5

0.4

0.3

0.2

0.1

500

1000

4000

3500

3000

2500

2000

1500

SYSTEM CLOCK (MHz)

3.3V ANALOG

3.3V DIGITAL

1.8V ANALOG

1.8V DIGITAL

100

10k

100k

10M

100M

FREQUENCY OFFSET (Hz)

–70

–90

–80

–100

–110

–120

–130

–140

–150

–160

–170

978MHz

305MHz

123MHz

497MHz

100

10k

100k

10M

100M

FREQUENCY OFFSET (Hz)

1396MHz ABSOLUTE

1396MHz RESIDUAL

–60

–90

–80

–70

–100

–110

–120

–130

–140

–150

–160

–60

–90

–80

–70

–100

–110

–120

–130

–140

–150

–160

–170

–180

100

10k

100k

10M

100M

FREQUENCY OFFSET (Hz)

1396MHz ABSOLUTE

1396MHz RESIDUAL

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