STBLC01QTR datasheet(28/40 Pages) STMICROELECTRONICS

28 / 40 page

Application design guidelines

STLBC01

28/40

DocID022984 Rev 2

Figure 8. Xtal block diagram

Low power consumption and fast startup time is achieved by choosing a quartz crystal with

a low load capacitance C0. A reasonable choice for capacitor C0 is 10 pF. The Xtal startup

time is typically 1 ms but can go up to 10 ms depending on the quality factor of the external

quartz chosen. To achieve good frequency stability, the following equation then needs to be

satisfied:

Equation 1

where C

= C

PCB1

+ C

PAD

, C

= C

PCB2

PAD

and C

are external (SMD)

components, C

PCB1

and C

PCB2

are PCB routing parasites and C

PAD

is the equivalent small-

signal pad-capacitance. The value of C

PAD

is around 1 pF for each pad. The routing

parasites should be minimized by placing quartz and C

/ C

close to the chip, not only for

an easier matching of the load capacitance C0, but also to ensure robustness against noise

injection. Connect each capacitor of the XTAL oscillator to ground by a separate via.

To achieve good noise immunity against external interference, the XTAL oscillator is

designed with low input impedance using a chip-internal 260 k

Ω resistor between XTAL1

and XTAL2. In case the noise robustness needs to be further increased, an external parallel

resistor can be added at the cost of extra current consumption.

Amplitude regulation

Buffered

rail-to-rail

clock

XTAL1

XTAL2

CPAD

CPB2

CPB1

AM10262V1

′

⋅

′

-----------------------

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