ADuCM361BCPZ128-R7 datasheet(16/24 Pages) AD

tên linh kiện	ADuCM361BCPZ128-R7

Giải thích chi tiết về linh kiện	Low Power, Precision Analog Microcontroller with Dual Sigma-Delta ADCs, ARM Cortex-M3

PDF	24 Pages

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nhà sản xuất	AD [Analog Devices]

Trang chủ	http://www.analog.com

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ADuCM360/ADuCM361

Data Sheet

Rev. B | Page 16 of 24

Table 13. SPI Slave Mode Timing

Parameter

Description

Min

Typ

Max

Unit

CS to SCLK edge

62.5

tSL

SCLK low pulse width1

(SPIDIV + 1) × tUCLK

tSH

SCLK high pulse width1

62.5

(SPIDIV + 1) × tUCLK

tDAV

Data output valid after SCLK edge

49.1

tDSU

Data input setup time before SCLK edge

20.2

tDHD

Data input hold time after SCLK edge

10.1

tDF

Data output fall time

35.5

tDR

Data output rise time

35.5

tSR

SCLK rise time

35.5

tSF

SCLK fall time

35.5

tDOCS

Data output valid after CS edge

tSFS

CS high after SCLK edge

1 tUCLK = 62.5 ns. It corresponds to the internal 16 MHz clock before the clock divider.

SCLK

(POLARITY = 0)

SCLK

(POLARITY = 1)

tSH

tSL

tSR

tSF

tSFS

MISO

MSB

BIT 6 TO BIT 1

LSB

MOSI

MSB IN

BIT 6 TO BIT 1

LSB IN

tDHD

tDSU

tDAV

tDR

tDF

tCS

Figure 6. SPI Slave Mode Timing (Phase Mode = 1)

SCLK

(POLARITY = 0)

SCLK

(POLARITY = 1)

tSH

tSL

tSR

tSF

tSFS

MISO

MSB

BIT 6 TO BIT 1

LSB

MOSI

MSB IN

BIT 6 TO BIT 1

LSB IN

tDHD

tDSU

tDAV

tDR

tDF

tDOCS

tCS

Figure 7. SPI Slave Mode Timing (Phase Mode = 0)

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