ADuCM361BCPZ128-R7 datasheet(15/24 Pages) AD

tên linh kiện	ADuCM361BCPZ128-R7

Giải thích chi tiết về linh kiện	Low Power, Precision Analog Microcontroller with Dual Sigma-Delta ADCs, ARM Cortex-M3

PDF	24 Pages

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nhà sản xuất	AD [Analog Devices]

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15 / 24 page

Data Sheet

ADuCM360/ADuCM361

Rev. B | Page 15 of 24

SPI TIMING SPECIFICATIONS

Table 12. SPI Master Mode Timing

Parameter

Description

Min

Typ

Max

Unit

tSL

SCLK low pulse width1

(SPIDIV + 1) × tUCLK

tSH

SCLK high pulse width1

(SPIDIV + 1) × tUCLK

tDAV

Data output valid after SCLK edge

35.5

tDOSU

Data output setup time before SCLK edge1

(SPIDIV + 1) × tUCLK

tDSU

Data input setup time before SCLK edge

58.7

tDHD

Data input hold time after SCLK edge

tDF

Data output fall time

35.5

tDR

Data output rise time

35.5

tSR

SCLK rise time

35.5

tSF

SCLK fall time

35.5

1 tUCLK = 62.5 ns. It corresponds to the internal 16 MHz clock before the clock divider.

SCLK

(POLARITY = 0)

1/2 SCLK

CYCLE

SCLK

(POLARITY = 1)

MOSI

MSB

BIT 6 TO BIT 1

LSB

MISO

MSB IN

BIT 6 TO BIT 1

LSB IN

tSH

tCS

tSL

3/4 SCLK

CYCLE

tSFS

tSR

tSF

tDR

tDF

tDAV

tDSU

tDHD

Figure 4. SPI Master Mode Timing (Phase Mode = 1)

SCLK

(POLARITY = 0)

SCLK

(POLARITY = 1)

MOSI

MSB

BIT 6 TO BIT 1

LSB

MISO

MSB IN

BIT 6 TO BIT 1

LSB IN

tSH

tSR

tSF

tDR

tDF

tDAV

tDOSU

tDSU

tDHD

1 SCLK CYCLE

tCS

tSL

1 SCLK CYCLE

SFS

Figure 5. SPI Master Mode Timing (Phase Mode = 0)

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