STM8S005K6 datasheet(81/103 Pages) STMICROELECTRONICS

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The reset network shown in the following figure protects the device against parasitic resets.

The user must ensure that the level on the NRST pin can go below VIL(NRST) max. (see Table

40: NRST pin characteristics ), otherwise the reset is not taken into account internally.

For power consumption sensitive applications, the external reset capacitor value can be

reduced to limit the charge/discharge current. If NRST signal is used to reset external circuitry,

attention must be taken to the charge/discharge time of the external capacitor to fulfill the

external devices reset timing conditions. Minimum recommended capacity is 100 nF.

Figure 37: Recommended reset pin protection

External

reset

circuit

(optional)

0.1 μF

NRST

VDD

RPU

Filter

Internal reset

STM8

SPI serial peripheral interface

9.3.9

Unless otherwise specified, the parameters given in the following table are derived from tests

performed under ambient temperature, fMASTER frequency and VDD supply voltage conditions.

tMASTER = 1/fMASTER.

Refer to I/O port characteristics for more details on the input/output alternate function

characteristics (NSS, SCK, MOSI, MISO).

Table 41: SPI characteristics

Unit

Max

Min

Conditions

Parameter

Symbol

MHz

Master mode

SPI clock

frequency

fSCK1

tc(SCK)

Slave mode

Capacitive load: C = 30 pF

SPI clock rise

and fall time

tr(SCK)

tf(SCK)

4 x

tMASTER

Slave mode

NSS setup time

tsu(NSS)

(1)

Slave mode

NSS hold time

th(NSS)

(1)

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DocID022186 Rev 3

Electrical characteristics

STM8S005K6 STM8S005C6

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