JS28F128P30TF75A datasheet(36/90 Pages) MICRON

36 / 90 page

P30-65nm SBC

Datasheet

Apr 2010

Order Number: 208033-02

11.2.2

Latency Count (RCR[13:11])

The Latency Count (LC) bits tell the device how many clock cycles must elapse from the

rising edge of ADV# (or from the first valid clock edge after ADV# is asserted) until the

first valid data word is driven onto DQ[15:0]. The input clock frequency is used to

determine this value and Figure 10 shows the data output latency for the different

settings of LC. The maximum Latency Count for P30-65nm SBC device would be Code 4

based on the Max clock frequency specification of 52MHz, and there will be zero WAIT

States when bursting within the word line. Please also refer to Section 11.2.3, “End of

Word Line (EOWL) Considerations” on page 37 for more information on EOWL.

Refer to Table 14, “LC and Frequency Support” on page 36 for Latency Code Settings.

Figure 10: First-Access Latency Count

Table 14: LC and Frequency Support

Latency Count Settings

Frequency Support (MHz)

≤ 40

≤ 52

Code1

(Reserved

Code6

Code5

Code4

Code3

Code2

Code0(Reserved)

Code7

Valid

Address

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Address[A]

ADV#[V]

15-0 [D/Q]

CLK[C]

15-0 [D/Q]

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