TLK105 datasheet(63/99 Pages) TI

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TLK105

TLK106

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SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013

Table 8-25. RMII Control and Status Register (RCSR), address 0x0017 (continued)

BIT

NAME

DEFAULT

DESCRIPTION

RMII Revision

0,RW

RMII Revision Select:

Select

1 = (RMII revision 1.0) CRS_DV will remain asserted until final data is transferred.

CRS_DV will not toggle at the end of a packet.

0 = (RMII revision 1.2) CRS_DV will toggle at the end of a packet to indicate de-

assertion of CRS.

RMII OVFL Status

0,COR

RX FIFO Over Flow Status:

1 = Normal

0 = Overflow detected

RMII OVFL Status

0,COR

RX FIFO Under Flow Status:

1 = Normal

0 = Underflow detected

1:0

ELAST_FUB

<01>,RW

Receive Elasticity Buffer Size:

This field controls the Receive Elasticity Buffer which allows for frequency variation

tolerance between the 50MHz RMII clock and the recovered data. The following values

indicate the tolerance in bits for a single packet. The minimum setting allows for standard

Ethernet frame sizes at ±50ppm accuracy for both RMII and Receive clocks. For greater

frequency tolerance the packet lengths may be scaled (for ±100ppm, divide the packet

lengths by 2).

00 = 14 bit tolerance (up to 16800 byte packets)

01 = 2 bit tolerance (up to 2400 byte packets)

10 = 6 bit tolerance (up to 7200 byte packets)

11 = 10 bit tolerance (up to 12000 byte packets)

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