MPC9600 REVISION 6 JANUARY 7, 2013

8

©2013 Integrated Device Technology, Inc.

MPC9600 Data Sheet

LOW VOLTAGE, 2.5V AND 3.3V LVCMOS PLL CLOCK DRIVER

Figure 3. Configuration for 126 MHz Clocks

Figure 4. Configuration for 133.3/66.67 MHz Clocks

Table 9. Typical and Maximum Period Jitter Specification

Device Configuration

QA0 to QA6

QB0 to QB6

QC0 to QC6

TypMax

TypMax

TypMax

All output banks in

2 (FSELA = 0 and FESLB = 0 and FSELC = 0)

4 (FSELA = 1 and FESLB = 1 and FSELC = 1)

1. In this configuration, all MPC9600 outputs generate the same clock frequency. See Figure 3 for an example configuration.

25

20

50

70

50

50

70

100

25

20

50

70

Mixed

for output banks in

2 divider configurations

for output banks in

4 divider configurations

2. Multiple frequency generation. Jitter data are specified for each output divider separately. See Figure 7 for an example.

80

25

130

70

100

60

150

100

80

25

130

70

Table 10. Typical and Maximum Cycle-to-Cycle Jitter Specification

Device Configuration

QA0 to QA6

QB0 to QB6

QC0 to QC6

TypMax

TypMax

TypMax

All output banks in

2 (FSELA = 0 and FESLB = 0 and FSELC = 0)

4 (FSELA = 1 and FESLB = 1 and FSELC = 1)

1. In this configuration, all MPC9600 outputs generate the same clock frequency.

40

40

90

110

80

120

130

180

40

40

90

110

Mixed

for output banks in

 2 divider configurations

for output banks in

 4 divider configurations

2. Multiple frequency generation. Jitter data are specified for each output divider separately.

150

30

250

110

200

120

280

180

150

30

250

110

MPC9600

125 MHz

125 MHz

20.833 MHz (Feedback)

125 MHz

CCLK

FB_IN

FSEL_FB

FSELA

FSELB

FSELC

QA0–6

QB0–6

QC0–6

QFB

7

7

7

1

0

0

0

Frequency Range

Min

Max

Input

16.67 MHz

33.33 MHz

QA outputs

100 MHz

200 MHz

QB outputs

100 MHz

200 MHz

QC outputs

100 MHz

200 MHz

Frequency Range

Min

Max

Input

25 MHz

50 MHz

QA outputs

100 MHz

200 MHz

QB outputs

100 MHz

200 MHz

QC outputs

100 MHz

200 MHz

MPC9600

133.3 MHz

66.67 MHz

33.33 MHz (Feedback)

66.67 MHz

CCLK

FB_IN

FSEL_FB

FSELA

FSELB

FSELC

QA0–6

QB0–6

QC0–6

QFB

7

7

7

0

0

1

1