MPC9600 REVISION 6 JANUARY 7, 2013

7

©2013 Integrated Device Technology, Inc.

MPC9600 Data Sheet

LOW VOLTAGE, 2.5V AND 3.3V LVCMOS PLL CLOCK DRIVER

APPLICATIONS INFORMATION

Programming the MPC9600

The MPC9600 clock driver outputs can be configured into

several divider modes. Additionally the external feedback of the

device allows for flexibility in establishing various input to output

frequency relationships. The selectable feedback divider of the

three output groups allows the user to configure the device for 1:2,

1:3, 1:4 and 1:6 input:output frequency ratios. The use of even

dividers ensure that the output duty cycle is always 50%. Table 8

illustrates the various output configurations, the table describes

the outputs using the input clock frequency CLK as a reference.

The feedback divider division settings establish the output

relationship, in addition, it must be ensured that the VCO will be

stable given the frequency of the outputs desired. The feedback

frequency should be used to situate the VCO into a frequency

range in which the PLL will be stable. The design of the PLL

supports output frequencies from 50 MHz to 200 MHz while the

VCO frequency range is specified from 200 MHz to 400 MHz and

should not be exceeded for stable operation.

1. Output frequency relationship with respect to input reference frequency CLK. The VCO frequency range is always 200–400.

Configuration Inputs

Input Frequency

Range CLK

[MHz]

Output Frequency Ratio and Range

FSEL_FB

FSELA

FSELB

FSELC

Ratio, QAx [MHz]

Ratio, QBx [MHz]

Ratio, QCx [MHz]

0

0

0

0

25.0–50.0

4•CLK (100–200)

4•CLK (100–200)

4•CLK

(100–200)

0

0

0

1

4•CLK (100–200)

4•CLK (100–200)

2•CLK (50.0–100)

0

0

1

0

4•CLK (100–200)

2•CLK (50.0–100)

4•CLK

(100–200)

0

0

1

1

4•CLK (100–200)

2•CLK (50.0–100)

2•CLK (50.0–100)

0

1

0

0

2•CLK (50.0–100)

4•CLK (100–200)

4•CLK

(100–200)

0

1

0

1

2•CLK (50.0–100)

4•CLK (100–200)

2•CLK (50.0–100)

0

1

1

0

2•CLK (50.0–100)

2•CLK (50.0–100)

4•CLK

(100–200)

0

1

1

1

2•CLK (50.0–100)

2•CLK (50.0–100)

2•CLK (50.0–100)

1

0

0

0

16.67–33.33

6•CLK (100–200)

6•CLK (100–200)

6•CLK

(100–200)

1

0

0

1

6•CLK (100–200)

6•CLK (100–200)

3•CLK (50.0–100)

1

0

1

0

6•CLK (100–200)

3•CLK (50.0–100)

6•CLK

(100–200)

1

0

1

1

6•CLK (100–200)

3•CLK (50.0–100)

3•CLK (50.0–100)

1

1

0

0

3•CLK (50.0–100)

6•CLK (100–200)

6•CLK

(100–200)

1

1

0

1

3•CLK (50.0–100)

6•CLK (100–200)

3•CLK (50.0–100)

1

1

1

0

3•CLK (50.0–100)

3•CLK (50.0–100)

6•CLK

(100–200)

1

1

1

1

3•CLK (50.0–100)

3•CLK (50.0–100)

3•CLK (50.0–100)