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DP83620 bảng dữ liệu(PDF) 2 Page - Texas Instruments |
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DP83620 bảng dữ liệu(HTML) 2 Page - Texas Instruments |
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2 / 105 page  DP83620 SNLS339C – JANUARY 2011 – REVISED APRIL 2013 www.ti.com 4.24 AC Specifications — Auto-Negotiation Fast Link 1 Introduction .............................................. 1 Pulse (FLP) Timing ................................. 23 1.1 Features ............................................. 1 4.25 AC Specifications — 100BASE-TX Signal Detect 1.2 Applications .......................................... 1 Timing .............................................. 24 1.3 Description ........................................... 1 4.26 AC Specifications — 100 Mb/s Internal Loopback 2 Device Information ...................................... 4 Timing .............................................. 24 2.1 System Diagram ..................................... 4 4.27 AC Specifications — 10 Mb/s Internal Loopback Timing .............................................. 25 2.2 Block Diagram ....................................... 4 4.28 AC Specifications — RMII Transmit Timing (Slave 3 Pin Descriptions ......................................... 5 Mode) ............................................... 25 3.1 Pin Layout ........................................... 6 4.29 AC Specifications — Transmit Timing (Master 3.2 PACKAGE PIN ASSIGNMENTS .................... 7 Mode) ............................................... 26 3.3 SERIAL MANAGEMENT INTERFACE .............. 8 4.30 AC Specifications — RMII Receive Timing (Slave 3.4 MAC DATA INTERFACE ............................ 8 Mode) ............................................... 27 3.5 CLOCK INTERFACE ................................ 9 4.31 AC Specifications — RMII Receive Timing (Master Mode) ............................................... 28 3.6 LED INTERFACE .................................... 9 4.32 AC Specifications — RX_CLK Timing (RMII Master 3.7 JTAG INTERFACE ................................. 10 Mode) ............................................... 28 3.8 RESET AND POWER DOWN ...................... 10 4.33 AC Specifications — CLK_OUT Timing (RMII Slave 3.9 STRAP OPTIONS .................................. 10 Mode) ............................................... 29 3.10 10 Mb/s AND 100 Mb/s PMD INTERFACE ........ 12 4.34 AC Specifications — Single Clock MII (SCMII) Transmit Timing .................................... 29 3.11 RESERVED PINS .................................. 12 4.35 AC Specifications — Single Clock MII (SCMII) 3.12 POWER SUPPLY PINS ............................ 12 Receive Timing ..................................... 30 4 Electrical Specifications ............................. 13 4.36 AC Specifications — 100 Mb/s X1 to TX_CLK 4.1 Absolute Maximum Ratings ........................ 13 Timing .............................................. 30 4.2 Recommended Operating Conditions .............. 13 5 Configuration ........................................... 31 4.3 AC and DC Specifications .......................... 13 5.1 MEDIA CONFIGURATION ......................... 31 4.4 DC Specifications .................................. 14 5.2 AUTO-NEGOTIATION .............................. 31 4.5 AC Specifications — Power Up Timing ............ 15 5.3 AUTO-MDIX ........................................ 34 4.6 AC Specifications — Reset Timing ................. 16 5.4 AUTO-CROSSOVER IN FORCED MODE ......... 34 4.7 AC Specifications — MII Serial Management Timing 5.5 PHY ADDRESS .................................... 34 ...................................................... 17 5.6 LED INTERFACE ................................... 35 4.8 AC Specifications — 100 Mb/s MII Transmit Timing 5.7 HALF DUPLEX vs. FULL DUPLEX ................ 37 ...................................................... 17 5.8 INTERNAL LOOPBACK ............................ 38 4.9 AC Specifications — 100 Mb/s MII Receive Timing 17 4.10 AC Specifications — 100BASE-TX and 100BASE- 5.9 POWER DOWN/INTERRUPT ...................... 38 FX MII Transmit Packet Latency Timing ........... 18 5.10 ENERGY DETECT MODE ......................... 38 4.11 AC Specifications — 100BASE-TX and 100BASE- 5.11 LINK DIAGNOSTIC CAPABILITIES ................ 39 FX MII Transmit Packet Deassertion Timing ....... 18 5.12 BIST ................................................ 43 4.12 AC Specifications — 100BASE-TX Transmit Timing 6 MAC Interface .......................................... 44 (tR/F & Jitter) ........................................ 19 6.1 MII INTERFACE .................................... 44 4.13 AC Specifications — 100BASE-TX and 100BASE- FX MII Receive Packet Latency Timing ............ 19 6.2 REDUCED MII INTERFACE ....................... 45 4.14 AC Specifications — 100BASE-TX and 100BASE- 6.3 SINGLE CLOCK MII MODE ........................ 46 FX MII Receive Packet Deassertion Timing ....... 20 6.4 IEEE 802.3u MII SERIAL MANAGEMENT 4.15 AC Specifications — 10 Mb/s MII Transmit Timing 20 INTERFACE ........................................ 47 4.16 AC Specifications — 10 Mb/s MII Receive Timing . 20 6.5 PHY CONTROL FRAMES ......................... 48 4.17 AC Specifications — 10BASE-T MII Transmit 6.6 PHY STATUS FRAMES ............................ 49 Timing (Start of Packet) ............................ 21 7 Architecture ............................................. 50 4.18 AC Specifications — 10BASE-T MII Transmit 7.1 100BASE-TX TRANSMITTER ...................... 50 Timing (End of Packet) ............................. 21 7.2 100BASE-TX RECEIVER .......................... 53 4.19 AC Specifications — 10BASE-T MII Receive Timing 7.3 100BASE-FX OPERATION ......................... 57 (Start of Packet) .................................... 22 7.4 10BASE-T TRANSCEIVER MODULE .............. 58 4.20 AC Specifications — 10BASE-T MII Receive Timing (End of Packet) ..................................... 22 8 Reset Operation ........................................ 61 4.21 AC Specifications — 10 Mb/s Heartbeat Timing ... 22 8.1 HARDWARE RESET ............................... 61 4.22 AC Specifications — 10 Mb/s Jabber Timing ...... 23 8.2 FULL SOFTWARE RESET ......................... 61 4.23 AC Specifications — 10BASE-T Normal Link Pulse 8.3 SOFT RESET ...................................... 61 Timing .............................................. 23 9 Design Guidelines ..................................... 62 2 Contents Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83620 |
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