M68ICS08GR datasheet(109/408 Pages) FREESCALE

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Clock Generator Module (CGMC)

Functional Description

MC68HC908GR8 — Rev 4.0

Technical Data

MOTOROLA

Clock Generator Module (CGMC)

109

c. In the PLL multiplier select register low (PMSL) and the PLL

multiplier select register high (PMSH), program the binary

equivalent of N.

d. In the PLL VCO range select register (PMRS), program the

binary coded equivalent of L.

e. In the PLL reference divider select register (PMDS), program

the binary coded equivalent of R.

Table 7-1 provides numeric examples (numbers are in hexadecimal

notation):

7.4.7 Special Programming Exceptions

The programming method described in Programming the PLL does not

account for three possible exceptions. A value of 0 for R, N, or L is

meaningless when used in the equations given. To account for these

exceptions:

•

A 0 value for R or N is interpreted exactly the same as a value of 1.

•

A 0 value for L disables the PLL and prevents its selection as the

source for the base clock.

(See Base Clock Selector Circuit.)

Table 7-1. Numeric Example

fBUS

fRCLK

2.0 MHz

32.768 kHz

2.4576 MHz

32.768 kHz

12C

2.5 MHz

32.768 kHz

132

4.0 MHz

32.768 kHz

1E9

4.9152 MHz

32.768 kHz

258

5.0 MHz

32.768 kHz

263

7.3728 MHz

32.768 kHz

384

8.0 MHz

32.768 kHz

3D1

Freescale Semiconductor, Inc.

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