M68ICS08GR datasheet(292/408 Pages) FREESCALE

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System Integration Module (SIM)

Technical Data

MC68HC908GR8 — Rev 4.0

292

System Integration Module (SIM)

MOTOROLA

Figure 19-17. Wait Recovery from Internal Reset

19.7.2 Stop Mode

In stop mode, the SIM counter is reset and the system clocks are

disabled. An interrupt request from a module can cause an exit from stop

mode. Stacking for interrupts begins after the selected stop recovery

time has elapsed. Reset or break also causes an exit from stop mode.

The SIM disables the clock generator module outputs (CGMOUT and

CGMXCLK) in stop mode, stopping the CPU and peripherals. Stop

recovery time is selectable using the SSREC bit in the mask option

normal delay of 4096 CGMXCLK cycles down to 32. This is ideal for

applications using canned oscillators that do not require long startup

times from stop mode.

NOTE:

External crystal applications should use the full stop recovery time by

clearing the SSREC bit.

A break interrupt during stop mode sets the SIM break stop/wait bit

(SBSW) in the SIM break status register (SBSR).

The SIM counter is held in reset from the execution of the STOP

instruction until the beginning of stop recovery. It is then used to time the

recovery period. Figure 19-18 shows stop mode entry timing.

NOTE:

To minimize stop current, all pins configured as inputs should be driven

to a logic 1 or logic 0.

IAB

IDB

RST

$A6

$6E0B

RSTVCTH RSTVCTL

$A6

CGMXCLK

CYCLES

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