M68ICS08GR datasheet(282/408 Pages) FREESCALE

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System Integration Module (SIM)

Technical Data

MC68HC908GR8 — Rev 4.0

282

System Integration Module (SIM)

MOTOROLA

19.5.3 SIM Counter and Reset States

External reset has no effect on the SIM counter. (See Stop Mode for

details.) The SIM counter is free-running after all reset states. (See

Active Resets from Internal Sources for counter control and internal

reset recovery sequences.)

19.6 Exception Control

Normal, sequential program execution can be changed in three different

ways:

•

Interrupts:

–

Maskable hardware CPU interrupts

–

Non-maskable software interrupt instruction (SWI)

•

Reset

•

Break interrupts

19.6.1 Interrupts

At the beginning of an interrupt, the CPU saves the CPU register

contents on the stack and sets the interrupt mask (I bit) to prevent

additional interrupts. At the end of an interrupt, the RTI instruction

recovers the CPU register contents from the stack so that normal

processing can resume. Figure 19-8 shows interrupt entry timing. Figure

19-9 shows interrupt recovery timing.

Interrupts are latched, and arbitration is performed in the SIM at the start

of interrupt processing. The arbitration result is a constant that the CPU

uses to determine which vector to fetch. Once an interrupt is latched by

the SIM, no other interrupt can take precedence, regardless of priority,

until the latched interrupt is serviced (or the I bit is cleared). See Figure

19-10.

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