M68ICS08GR datasheet(239/408 Pages) FREESCALE

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Serial Communications Interface (SCI)

Functional Description

MC68HC908GR8 — Rev 4.0

Technical Data

MOTOROLA

Serial Communications Interface (SCI)

239

continuously loads break characters into the transmit shift register. After

software clears the SBK bit, the shift register finishes transmitting the

last break character and then transmits at least one logic 1. The

automatic logic 1 at the end of a break character guarantees the

recognition of the start bit of the next character.

The SCI recognizes a break character when a start bit is followed by

eight or nine logic 0 data bits and a logic 0 where the stop bit should be.

Receiving a break character has these effects on SCI registers:

•

Sets the framing error bit (FE) in SCS1

•

Sets the SCI receiver full bit (SCRF) in SCS1

•

Clears the SCI data register (SCDR)

•

Clears the R8 bit in SCC3

•

Sets the break flag bit (BKF) in SCS2

•

May set the overrun (OR), noise flag (NF), parity error (PE), or

reception in progress flag (RPF) bits

18.5.2.4 Idle Characters

An idle character contains all logic 1s and has no start, stop, or parity bit.

Idle character length depends on the M bit in SCC1. The preamble is a

synchronizing idle character that begins every transmission.

If the TE bit is cleared during a transmission, the PE2/TxD pin becomes

idle after completion of the transmission in progress. Clearing and then

setting the TE bit during a transmission queues an idle character to be

sent after the character currently being transmitted.

NOTE:

When queueing an idle character, return the TE bit to logic 1 before the

stop bit of the current character shifts out to the TxD pin. Setting TE after

the stop bit appears on TxD causes data previously written to the SCDR

to be lost.

Toggle the TE bit for a queued idle character when the SCTE bit

becomes set and just before writing the next byte to the SCDR.

Freescale Semiconductor, Inc.

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