MPC8260EC datasheet(17/41 Pages) FREESCALE

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MPC8260 PowerQUICC II Integrated Communications Processor Hardware Specifications, Rev. 2

Freescale Semiconductor

Electrical and Thermal Characteristics

Table 10 lists SIU output characteristics.

Activating data pipelining (setting BRx[DR] in the memory controller)

improves the AC timing. When data pipelining is activated, sp12 can be

used for data bus setup even when ECC or PARITY are used. Also, sp33a

can be used as the AC specification for DP signals.

Figure 8 shows TDM input and output signals.

Figure 8. TDM Signal Diagram

Table 10. AC Characteristics for SIU Outputs1

1 Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings are

measured at the pin.

NOTE

Spec Number

Characteristic

Max Delay (ns)

Min Delay (ns)

Max

Min

66 MHz

sp31

sp30

PSDVAL/TEA/TA

0.5

sp32

sp30

ADD/ADD_atr./BADDR/CI/GBL/WT

0.5

sp33a

sp30

Data bus

0.5

sp33b

sp30

0.5

sp34

sp30

memc signals/ALE

0.5

sp35

sp30

all other signals

7.5

0.5

Note:

Serial CLKin

TDM input signals

TDM output signals

sp20

sp21

sp40/sp41

Note: There are four possible TDM timing conditions:

1. Input sampled on the rising edge and output driven on the rising edge (shown).

2. Input sampled on the rising edge and output driven on the falling edge.

3. Input sampled on the falling edge and output driven on the falling edge.

4. Input sampled on the falling edge and output driven on the rising edge.

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