MC68331TS datasheet(24/84 Pages) FREESCALE

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MC68331TS/D

When the on-chip clock synthesizer is used, system clock frequency is controlled by the bits in the upper

byte of SYNCR. Bits in the lower byte show status of or control operation of internal and external clocks.

The SYNCR can be read or written only when the CPU is operating at the supervisor privilege level.

W —Frequency Control (VCO)

This bit controls a prescaler tap in the synthesizer feedback loop. Setting the bit increases the VCO

speed by a factor of four. VCO relock delay is required.

X —Frequency Control Bit (Prescale)

This bit controls a divide by two prescaler that is not in the synthesizer feedback loop. Setting the bit

doubles clock speed without changing the VCO speed. There is no VCO relock delay.

Y[5:0] —Frequency Control (Counter)

The Y field controls the modulus down counter in the synthesizer feedback loop, causing it to divide by

a value of Y

+ 1. Values range from 0 to 63. VCO relock delay is required.

EDIV —E Clock Divide Rate

0 = ECLK frequency is system clock divided by 8.

1 = ECLK frequency is system clock divided by 16.

ECLK is an external M6800 bus clock available on pin ADDR23. Refer to 3.5 Chip Selects for more in-

formation.

SLIMP —Limp Mode Flag

0 = External crystal is VCO reference.

1 = Loss of crystal reference.

When the on-chip synthesizer is used, loss of reference frequency causes SLIMP to be set. The VCO

continues to run using the base control voltage. Maximum limp frequency is maximum specified system

clock frequency. X-bit state affects limp frequency.

SLOCK —Synthesizer Lock Flag

0 = VCO is enabled, but has not locked.

1 = VCO has locked on the desired frequency (or system clock is external).

The MCU maintains reset state until the synthesizer locks, but SLOCK does not indicate synthesizer

lock status until after the user writes to SYNCR.

RSTEN —Reset Enable

0 = Loss of crystal causes the MCU to operate in limp mode.

1 = Loss of crystal causes system reset.

STSIM —Stop Mode SIM Clock

0 = When LPSTOP is executed, the SIM clock is driven from the crystal oscillator and the VCO is

turned off to conserve power.

1 = When LPSTOP is executed, the SIM clock is driven from the VCO.

STEXT —Stop Mode External Clock

0 = When LPSTOP is executed, the CLKOUT signal is held negated to conserve power.

1 = When LPSTOP is executed, the CLKOUT signal is driven from the SIM clock, as determined by

the state of the STSIM bit.

3.4 External Bus Interface

The external bus interface (EBI) transfers information between the internal MCU bus and external de-

vices. The external bus has 24 address lines and 16 data lines.

The EBI provides dynamic sizing between 8-bit and 16-bit data accesses. It supports byte, word, and

long-word transfers. Ports are accessed through the use of asynchronous cycles controlled by the data

transfer (SIZ1 and SIZ0) and data size acknowledge pins (DSACK1 and DSACK0). Multiple bus cycles

may be required for a transfer to or from an 8-bit port.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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