ADS58C28IRGC datasheet(7/67 Pages) TI

7 / 67 page

ADS58C28

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SBAS509B – JUNE 2010 – REVISED OCTOBER 2010

DIGITAL CHARACTERISTICS

The DC specifications refer to the condition where the digital outputs are not switching, but are permanently at valid logic

level 0 or 1. AVDD = 1.8V and DRVDD = 1.8V.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DIGITAL INPUTS—RESET, SCLK, SDATA, SEN, CTRL1, CTRL2, and CTRL3

High-level input voltage

1.3

RESET, SCLK, SDATA and SEN support

1.8V and 3.3V CMOS logic levels.

Low-level input voltage

0.4

SDATA, SCLK(1)

VHIGH = 1.8V

µA

High-level input

current

SEN(2)

VHIGH = 1.8V

µA

SDATA, SCLK

VLOW = 0V

µA

Low-level input

current

SEN

VLOW = 0V

–10

µA

DIGITAL OUTPUTS—CMOS INTERFACE (CHx_Dn, SDOUT)

High-level output voltage

DRVDD – 0.1

DRVDD

Low-level output voltage

0.1

DIGITAL OUTPUTS—LVDS INTERFACE (CHxP/M, CLKOUTP/M)

VODH, High-level output voltage

(3)

Standard swing LVDS

270

350

430

VODL, Low-level output voltage

(3)

Standard swing LVDS

–430

–350

–270

VODH, High-level output voltage

(3)

Low swing LVDS(4)

200

VODL, Low-level output voltage

(3)

Low swing LVDS(4)

–200

VOCM, Output common-mode voltage

0.9

1.05

1.25

(1)

SDATA and SCLK have an internal 150k

Ω pull-down resistor.

(2)

SEN has an internal 150k

Ω pull-up resistor to AVDD.

(3)

With external 100

Ω termination.

(4)

See the LVDS Output Data and Clock Buffers section.

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