HT85F2270 datasheet(199/226 Pages) HOLTEK

199 / 226 page

Rev. 1.00

199 of ��6

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Standard 8051 8-Bit Flash MCU

HT85F2260/HT85F2270/HT85F2280

Basic UART Data Transfer Scheme

The block diagram shows the overall UART data transfer structure arrangement. For data

transmission, the actual data to be transmitted from the MCU is first transferred to the transmitted

from where it will be shifted out, LSB first, onto the transmitter pin, TXDn, at a rate controlled by

the Baud Rate Generator. Only the transmitted register is mapped onto the MCU Data Memory, the

Transmit Shift Register is not mapped and is therefore inaccessible to the application program.

For data reception, data to be received by the UART is accepted on the external receive pin,

RXDn, from where it is shifted in, LSB first, to the Receiver Shift Register at a rate controlled

by the Baud Rate Generator. When the shift register is full, the data will then be transferred from

the shift register to the internal received register, where it is buffered and can be manipulated by

the application program. Only the received register is mapped onto the MCU Data Memory, the

Receiver Shift Register is not mapped and is therefore inaccessible to the application program.

It should be noted that the actual register for data transmission and reception, only exists as a single

shared register in the Data Memory, known as the S0BUF register in the UART0 or the S1BUF

Tr an sm it R eg is te r

Re ce iv e Re gi st er

MS B

LS B

Tr an sm i tte r S hi ft Re gi st er

Tr an sm it

TX Dn P in

MS B

LS B

Re ce iv er Sh i ft R eg is te r

Re ce iv e

RX Dn P in

Ba ud R at e

Ge ner at or

CL KC LK

Bu ff er

MC U Da ta B us

Basic UART Data Transfer Diagram

HT85F2270 bảng dữ liệu(PDF) 199 Page - Holtek Semiconductor Inc