HT85F2270 datasheet(184/226 Pages) HOLTEK

184 / 226 page

Rev. 1.00

184 of ��6

�a� 1�� 01�

Standard 8051 8-Bit Flash MCU

HT85F2260/HT85F2270/HT85F2280

I2C Bus Data and Acknowledge Signal

The transmitted data is 8-bits wide and is transmitted after the slave device has acknowledged

receipt of its slave address. The order of serial bit transmission is the MSB first and the LSB last.

After receipt of 8-bits of data, the receiver must transmit an acknowledge signal, a low level, before

it can receive the next data byte. If the slave transmitter does not receive an acknowledge bit signal

from the master receiver, then the slave transmitter will release the SDA line to allow the master to

send a STOP signal to release the I2C Bus. The corresponding data will be stored in the I2CDAT

the I2CDAT register. If setup as a receiver, the slave device must read the transmitted data from the

I2CDAT register.

The AA bit in the I2CCON register bit indicates the type of acknowledge returned during the

acknowledge cycle on the SCL pin. If this bit is cleared to zero, a "not acknowledge" (high level

on SDA) is returned during the acknowledge cycle. If the bit is set to high, an "acknowledge" (low

level on SDA) is returned during the acknowledge cycle. The slave device, which is setup as a

transmitter will check the AA bit in the I2CCON register to determine if it is to send another data

byte, if not then it will release the SDA line and await the receipt of a STOP signal from the master.

Note: * When a slave address is matched� the device must be placed in either the transmit mode

and then write data to the I�CDAT register� or in the receive mode where it must implement a

dumm� read from the I�CDAT register to release the SCL line.

I2C Communication Timing Diagram

HT85F2270 bảng dữ liệu(PDF) 184 Page - Holtek Semiconductor Inc