HT85F2270 datasheet(183/226 Pages) HOLTEK

183 / 226 page

Rev. 1.00

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Standard 8051 8-Bit Flash MCU

HT85F2260/HT85F2270/HT85F2280

I2C Bus Start Signal

The START signal can only be generated by the master device connected to the I2C bus and not by

the slave device. This START signal will be detected by all devices connected to the I2C bus. When

detected, this indicates that the I2C bus is busy and therefore the STA bit will be set. A START

condition occurs when a high to low transition on the SDA line takes place when the SCL line

remains high.

Slave Address

The transmission of a START signal by the master will be detected by all devices on the I2C bus.

To determine which slave device the master wishes to communicate with, the address of the slave

device will be sent out immediately following the START signal. All slave devices, after receiving

this 7-bit address data, will compare it with their own 7-bit slave address. If the address sent out

by the master matches the internal address of the microcontroller slave device, or if the general

call address, 00H, is received when the GC bit in the I2CADR register is set high, then an internal

I2C bus interrupt signal will be generated. The next bit following the address, which is the 8th bit,

defines the read/write status. The slave device will then transmit an acknowledge bit, which is a

low level, as the 9th bit. The slave device will also set the flag SI when the addresses match.

As an I2C bus interrupt will take place if one of the possible I2C states is matched when the

program enters the interrupt subroutine, the I2CSTA register should be examined to see, for

example, whether the interrupt source has come from a matching slave address or from the

completion of a data byte transfer. When a slave address is matched, the device must be placed

in either the transmit mode and then data written to the I2CDAT register, or in the receive mode

where it must implement a dummy read from the I2CDAT register to release the SCL line. Refer to

the I2C Status Code section for details.

I2C Bus Read/Write Signal

The Read/Write bit, so called as R/W bit, is located in the 8th bit of the address data in the I2CDAT

operation. The direction bit defines whether the slave device wishes to read data from the I2C bus

or write data to the I2C bus. The slave device should examine this bit to determine if it is to be a

transmitter or a receiver. If the R/W bit is “1” then this indicates that the master device wishes to

read data from the I2C bus, therefore the slave device must be setup to send data to the I2C bus as a

transmitter. If the R/W bit is “0” then this indicates that the master wishes to send data to the I2C

bus, therefore the slave device must be setup to read data from the I2C bus as a receiver.

I2C Bus Slave Address Acknowledge Signal

After the master has transmitted a calling address, any slave device on the I2C bus, whose

own internal address matches the calling address, must generate an acknowledge signal. The

acknowledge signal will inform the master that a slave device has accepted its calling address. If no

acknowledge signal is received by the master then a STOP signal must be transmitted by the master

to end the communication. When the SI flag is high, the addresses have matched and the slave

device must check the R/W bit, to determine if it is to be a transmitter or a receiver. If the R/W

bit is high, the slave device should be setup to be a transmitter, and then the microcontroller slave

device should be setup as a receiver.

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