M24256-DRMN6TP datasheet(9/40 Pages) STMICROELECTRONICS

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Signal description

Doc ID 6757 Rev 30

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2.6

Supply voltage (VCC)

2.6.1

Operating supply voltage VCC

Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage

within the specified [VCC(min), VCC(max)] range must be applied (see Operating conditions

in Section 8: DC and AC parameters). In order to secure a stable DC supply voltage, it is

recommended to decouple the VCC line with a suitable capacitor (usually of the order of

10 nF to 100 nF) close to the VCC/VSS package pins.

This voltage must remain stable and valid until the end of the transmission of the instruction

and, for a write instruction, until the completion of the internal write cycle (tW).

2.6.2

Power-up conditions

The VCC voltage has to rise continuously from 0 V up to the minimum VCC operating voltage

(see Operating conditions in Section 8: DC and AC parameters) and the rise time must not

vary faster than 1 V/µs.

2.6.3

Device reset

In order to prevent inadvertent write operations during power-up, a power-on-reset (POR)

circuit is included.

At power-up, the device does not respond to any instruction until VCC has reached the

internal reset threshold voltage. This threshold is lower than the minimum VCC operating

voltage (see Operating conditions in Section 8: DC and AC parameters). When VCC passes

over the POR threshold, the device is reset and enters the Standby Power mode; however,

the device must not be accessed until VCC reaches a valid and stable DC voltage within the

specified [VCC(min), VCC(max)] range (see Operating conditions in Section 8: DC and AC

parameters).

In a similar way, during power-down (continuous decrease in VCC), the device must not be

accessed when VCC drops below VCC(min). When VCC drops below the power-on-reset

threshold voltage, the device stops responding to any instruction sent to it.

2.6.4

Power-down conditions

During power-down (continuous decrease in VCC), the device must be in the Standby Power

mode (mode reached after decoding a Stop condition, assuming that there is no internal

write cycle in progress).

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