DSPIC33FJ64GS406 datasheet(349/456 Pages) MICROCHIP

349 / 456 page

 2009-2012 Microchip Technology Inc.

DS70591E-page 349

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610

24.2

On-Chip Voltage Regulator

The

dsPIC33FJ32GS406/606/608/610

and

dsPIC33FJ64GS406/606/608/610 devices power

their core digital logic at a nominal 2.5V. This can create

a conflict for designs that are required to operate at a

higher typical voltage, such as 3.3V. To simplify system

design, all devices in the dsPIC33FJ32GS406/606/608/

610 and dsPIC33FJ64GS406/606/608/610 families

incorporate an on-chip regulator that allows the device to

run its core logic from VDD.

The regulator provides power to the core from the other

VDD pins. When the regulator is enabled, a low-ESR

(less than 5 ohms) capacitor (such as tantalum or

ceramic) must be connected to the VCAP pin

(Figure 24-1). This helps to maintain the stability of the

regulator. The recommended value for the filter

capacitor is provided in Table 27-13, located in

Section 27.1 “DC Characteristics”.

On a POR

, it takes approximately 20 s for the on-chip

voltage regulator to generate an output voltage. During

this time, designated as TSTARTUP, code execution is

disabled. TSTARTUP is applied every time the device

resumes operation after any power-down.

FIGURE 24-1:

CONNECTIONS FOR THE

ON-CHIP VOLTAGE

REGULATOR(1,2,3)

24.3

Brown-out Reset (BOR)

The Brown-out Reset (BOR) module is based on an

internal voltage reference circuit. The main purpose of

the BOR module is to generate a device Reset when a

brown-out condition occurs. Brown-out conditions are

generally caused by glitches on the AC mains (for

example, missing portions of the AC cycle waveform

due to bad power transmission lines, or voltage sags

due to excessive current draw when a large inductive

load is turned on).

A BOR generates a Reset pulse, which resets the

device. The BOR selects the clock source based on the

device Configuration bit values (FNOSC<2:0> and

POSCMD<1:0>).

If an oscillator mode is selected, the BOR activates the

Oscillator Start-up Timer (OST). The system clock is

held until OST expires. If the PLL is used, the clock is

held until the LOCK bit (OSCCON<5>) is ‘1’.

Concurrently, the Power-up Timer (PWRT) Time-out

(TPWRT) is applied before the internal Reset is

released. If TPWRT = 0 and a crystal oscillator is being

used, then a nominal delay of TFSCM = 100 is applied.

The total delay in this case is TFSCM.

The BOR status bit (RCON<1>) is set to indicate that a

BOR has occurred. The BOR circuit continues to

operate while in Sleep or Idle modes and resets the

device should VDD fall below the BOR threshold

voltage.

24.4

Watchdog Timer (WDT)

For

dsPIC33FJ32GS406/606/608/610

and

dsPIC33FJ64GS406/606/608/610 devices, the WDT

is driven by the LPRC oscillator. When the WDT is

enabled, the clock source is also enabled.

24.4.1

PRESCALER/POSTSCALER

The nominal WDT clock source from LPRC is

32.767 kHz. This feeds a prescaler that can be config-

ured for either 5-bit (divide-by-32) or 7-bit (divide-by-128)

operation. The prescaler is set by the WDTPRE Config-

uration bit. With a 32.767 kHz input, the prescaler yields

a nominal WDT Time-out (TWDT) period of 1 ms in 5-bit

mode or 4 ms in 7-bit mode.

A variable postscaler divides down the WDT prescaler

output and allows for a wide range of time-out periods.

The postscaler is controlled by the WDTPOST<3:0>

Configuration bits (FWDT<3:0>), which allow the

selection of 16 settings, from 1:1 to 1:32,768. Using the

prescaler and postscaler, time-out periods, ranging

from 1 ms to 131 seconds, can be achieved.

Note:

It is important for the low-ESR capacitor to

be placed as close as possible to the VCAP

pin.

Note 1:

These are typical operating voltages. Refer

to Table 27-13 located in Section 27.1 “DC

Characteristics” for the full operating

ranges of VDD.

It is important for the low-ESR capacitor to

be placed as close as possible to the VCAP

pin.

Typical VCAP pin voltage = 2.5V when

VDD

 VDDMIN.

VDD

VCAP

VSS

dsPIC33F

CEFC

3.3V

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