DSPIC33FJ64GS406 datasheet(279/456 Pages) MICROCHIP

279 / 456 page

 2009-2012 Microchip Technology Inc.

DS70591E-page 279

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610

bit 5

ADDEN: Address Character Detect bit (bit 8 of received data = 1)

1 = Address Detect mode is enabled; if 9-bit mode is not selected, this does not take effect

0 = Address Detect mode is disabled

bit 4

RIDLE: Receiver Idle bit (read-only)

1 = Receiver is Idle

0 = Receiver is active

bit 3

PERR: Parity Error Status bit (read-only)

1 = Parity error has been detected for the current character (character at the top of the receive FIFO)

0 = Parity error has not been detected

bit 2

FERR: Framing Error Status bit (read-only)

1 = Framing error has been detected for the current character (character at the top of the receive

FIFO)

0 = Framing error has not been detected

bit 1

OERR: Receive Buffer Overrun Error Status bit (clear/read-only)

1 = Receive buffer has overflowed

0 = Receive buffer has not overflowed; clearing a previously set OERR bit (1  0 transition) will reset

the receiver buffer and the UxRSR to the empty state

bit 0

URXDA: UARTx Receive Buffer Data Available bit (read-only)

1 = Receive buffer has data, at least one more character can be read

0 = Receive buffer is empty

UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED)

Note 1: Refer to Section 17. “UART” (DS70188) in the “dsPIC33F/PIC24H Family Reference Manual” for

information on enabling the UART module for transmit operation. That section of the manual is available

on the Microchip web site, www.microchip.com.

dsPIC33FJ64GS406 bảng dữ liệu(PDF) 279 Page - Microchip Technology