DSPIC33FJ64GS406 datasheet(248/456 Pages) MICROCHIP

248 / 456 page

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610

DS70591E-page 248

 2009-2012 Microchip Technology Inc.

R/W-0

PENH

PENL

POLH

POLL

PMOD<1:0>(1)

OVRENH

OVRENL

bit 15

bit 8

R/W-0

OVRDAT<1:0>

FLTDAT<1:0>(2)

CLDAT<1:0>(2)

SWAP

OSYNC

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 15

PENH: PWMxH Output Pin Ownership bit

1 = PWM module controls PWMxH pin

0 = GPIO module controls PWMxH pin

bit 14

PENL: PWMxL Output Pin Ownership bit

1 = PWM module controls PWMxL pin

0 = GPIO module controls PWMxL pin

bit 13

POLH: PWMxH Output Pin Polarity bit

1 = PWMxH pin is active-low

0 = PWMxH pin is active-high

bit 12

POLL: PWMxL Output Pin Polarity bit

1 = PWMxL pin is active-low

0 = PWMxL pin is active-high

bit 11-10

PMOD<1:0>: PWM # I/O Pin Mode bits(1)

11 = PWM I/O pin pair is in the True Independent Output mode

10 = PWM I/O pin pair is in the Push-Pull Output mode

01 = PWM I/O pin pair is in the Redundant Output mode

00 = PWM I/O pin pair is in the Complementary Output mode

bit 9

OVRENH: Override Enable for PWMxH Pin bit

1 = OVRDAT<1> provides data for output on PWMxH pin

0 = PWM generator provides data for output on PWMxH pin

bit 8

OVRENL: Override Enable for PWMxL Pin bit

1 = OVRDAT<0> provides data for output on PWMxL pin

0 = PWM generator provides data for output on PWMxL pin

bit 7-6

OVRDAT<1:0>: Data for PWMxH, PWMxL Pins if Override is Enabled bits

If OVERENH = 1, OVRDAT<1> provides data for PWMxH

If OVERENL = 1, OVRDAT<0> provides data for PWMxL

bit 5-4

FLTDAT<1:0>: State for PWMxH and PWMxL Pins if FLTMOD is Enabled bits(2)

IFLTMOD (FCLCONx<15>) = 0: Normal Fault mode:

If Fault is active, then FLTDAT<1> provides the state for PWMxH.

If Fault is active, then FLTDAT<0> provides the state for PWMxL.

IFLTMOD (FCLCONx<15>) = 1: Independent Fault mode:

If current-limit is active, then FLTDAT<1> provides the state for PWMxH.

If Fault is active, then FLTDAT<0> provides the state for PWMxL.

Note 1: These bits should not be changed after the PWM module is enabled (PTEN = 1).

2: State represents the active/inactive state of the PWM depending on the POLH and POLL bit settings.

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