DSPIC33FJ64GS406 datasheet(213/456 Pages) MICROCHIP

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 2009-2012 Microchip Technology Inc.

DS70591E-page 213

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610

11.2

Open-Drain Configuration

In addition to the PORT, LAT and TRIS registers for

data control, some digital-only port pins can also be

individually configured for either digital or open-drain

output. This is controlled by the Open-Drain Control

of the bits configures the corresponding pin to act as an

open-drain output.

The open-drain feature allows the generation of

outputs higher than VDD (for example, 5V) on any

desired 5V tolerant pins by using external pull-up

resistors. The maximum open-drain voltage allowed is

the same as the maximum VIH specification.

Refer to “Pin Diagrams” for the available pins and

their functionality.

11.3

Configuring Analog Port Pins

The ADPCFG and TRIS registers control the operation

of the analog-to-digital port pins. The port pins that are

to function as analog inputs must have their corre-

sponding TRIS bit set (input). If the TRIS bit is cleared

(output), the digital output level (VOH or VOL) will be

converted.

The ADPCFG and ADPCFG2 registers have a default

value of 0x000; therefore, all pins that share ANx

functions are analog (not digital) by default.

When the PORT register is read, all pins configured as

analog input channels will read as cleared (a low level).

Pins configured as digital inputs will not convert an

analog input. Analog levels on any pin defined as a

digital input (including the ANx pins) can cause the

input buffer to consume current that exceeds the

device specifications.

11.4

I/O Port Write/Read Timing

One instruction cycle is required between a port direction

change or port write operation and a read operation of

the same port. Typically, this instruction would be a NOP.

An example is shown in Example 11-1.

11.5

Input Change Notification

The input change notification function of the I/O

ports allows the dsPIC33FJ32GS406/606/608/610

and dsPIC33FJ64GS406/606/608/610 devices to gen-

erate interrupt requests to the processor in response to

a Change-of-State (COS) on selected input pins. This

feature can detect input Change-of-States even in

Sleep mode, when the clocks are disabled. Depending

on the device pin count, up to 30 external signals (CNx

pin) can be selected (enabled) for generating an

interrupt request on a Change-of-State.

Four control registers are associated with the CN

module. The CNEN1 and CNEN2 registers contain the

interrupt enable control bits for each of the CN input

pins. Setting any of these bits enables a CN interrupt

for the corresponding pins.

Each CN pin also has a weak pull-up connected to it.

The pull-ups act as a current source connected to the

pin, and eliminate the need for external resistors when

the push button or keypad devices are connected. The

pull-ups are enabled separately using the CNPU1 and

CNPU2 registers, which contain the control bits for

each of the CN pins. Setting any of the control bits

enables the weak pull-ups for the corresponding pins.

EQUATION 11-1:

PORT WRITE/READ EXAMPLE

Note:

Pull-ups on change notification pins

should always be disabled when the port

pin is configured as a digital output.

MOV

0xFF00, W0

; Configure PORTB<15:8> as inputs

MOV

W0, TRISBB

; and PORTB<7:0> as outputs

NOP

; Delay 1 cycle

BTSS

PORTB, #13

; Next Instruction

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