QG5000XSL9TH datasheet(52/458 Pages) INTEL

52 / 458 page

Intel® 5000X Chipset Memory Controller Hub (MCH) Datasheet

3.5.2

CFGDAT: Configuration Data Register

CFGDAT provides data for the 4 bytes of configuration space defined by CFGADR. This

and CFGADR.CFGE (configuration enable) bit is set. The byte enables with the I/O

access define how many configuration bytes are accessed.

3.6

MCH Fixed Memory Mapped Registers

These registers are mapped into the fixed chipset specific range located from FE60

0000h - FE6F FFFFh.These appear at fixed addresses to support the boot process.

These registers also appear in the regular PCI Express configuration space.

The following table defines the memory address of the registers in this region.

Table 3-6.

I/O Address: CFCh

Bit

Attr

Default

Description

31:0

Configuration Data Window

The data written or read to the configuration register (if any) specified by

CFGADR

Table 3-7.

Mapping for Fixed Memory Mapped Registers

Memory Address

BOFL0

FE60_C000

BOFL1

FE60_C400

BOFL2

FE60_C800

BOFL3

FE60_CC00

SPAD0

FE60_D000

SPAD1

FE60_D400

SPAD2

FE60_D800

SPAD3

FE60_DC00

SPADS0

FE60_E000

SPADS1

FE60_E400

SPADS2

FE60_E800

SPADS3

FE60_EC00

AMBASE[31:0]

FE61_4800

AMBASE[63:32]

FE61_4C00

HECBASE

FE61_6400

QG5000XSL9TH bảng dữ liệu(PDF) 52 Page - Intel Corporation

QG5000XSL9TH bảng dữ liệu(HTML) 52 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL