QG5000XSL9TH datasheet(79/458 Pages) INTEL

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Intel® 5000X Chipset Memory Controller Hub (MCH) Datasheet

3.8.1.5

HDR - Header Type Register

This register identifies the header layout of the configuration space.

Device:

0, 2-3, 8, 9

Function:

Offset:

0Eh

Version:

Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset

Device:

4-5

Function:

Offset:

0Eh

Version:

Intel 5000Z Chipset

Device:

4-7

Function:

Offset:

0Eh

Version:

Intel 5000P Chipset

Device:

Function:

0, 2

Offset:

0Eh

Version:

Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset

Device:

Function:

Offset:

0Eh

Version:

Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset

Device:

Function:

Offset:

0Eh

Version:

Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset

Device:

Function:

Offset:

0Eh

Version:

Intel 5000P Chipset

Bit

Attr

Default

Description

7RO

(DEV16)

{1h}

else

{0h}

endif

Multi-function Device.

Selects whether this is a multi-function device, that may have alternative

configuration layouts. This bit is hardwired to ‘0’ for devices for the MCH with the

exception of device 16 fn 0-2, which it is set to ‘1’.

6:0

(DEV2-7)

{01h}

else

{00h}

endif

Configuration Layout.

This field identifies the format of the configuration header layout for a PCI-to-PCI

bridge from bytes 10h through 3Fh.

For PCI Express Devices 2,3,4,5,6,7 default is 01h, indicating “PCI to PCI Bridge”

For all other Devices: 0,8,9,16,17,21,22 default is 00h, indicating a conventional

type 00h PCI header

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