ISL75052SEH

3

FN8456.0

May 29, 2013

Pin Configuration

ISL75052SEH

(16 Ld CDFP)

TOP VIEW

2

3

4

5

6

7

8

116

15

14

13

12

11

10

9

VOUT

VOUT

VIN

VIN

VIN

NC

NC

OCP

BYP

ADJ

EN

GND

COMP

PG

VCCX

TMODE

DOTTED LINE SHOWS METAL BOTTOM

Pin Descriptions

PIN NUMBER

PIN NAME

DESCRIPTION

ESD CIRCUIT

3, 4, 5

VIN

Input supply pins.

Circuit 1

10

PG

is not in regulation.

Circuit 2

13

GND

GND pin. Pin 13 is also connected to the metal lid of the package.

Circuit 2

9

VCCX

The 3.8V internal bus is pinned out to accept a decoupling capacitor. Connect a 0.1µF

ceramic capacitor from VCCX pin to GND.

Circuit 2

1, 2

VOUT

Output voltage pins.

Circuit 1

12

COMP

Add compensation capacitor & resistor between COMP and GND.

Circuit 2

15

ADJ

Circuit 2

6, 7

NC

No connect. May be grounded if needed.

Circuit 2

16

BYP

Connect a 0.1µF capacitor from BYP pin to GND, to filter the internal VREF.

Circuit 2

8

OCP

OCP pin allows the Current limit to be programmed with an external resistor.

Circuit 2

14

EN

Circuit 2

11

TMODE

Test Mode pin, must be connected to GND.

Circuit 2

Bottom

Metallization

The metal surface on the bottom surface of the package is floating. For mounting

instructions see “Bottom Metal Mounting Guidelines” on page 8.

Circuit 2

PAD

GND

ESD CIRCUIT 1

ESD_CL_12V

PAD

GND

ESD_RC_7V

ESD CIRCUIT 2