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W25Q128FVCIP bảng dữ liệu(PDF) 85 Page - Winbond

tên linh kiện W25Q128FVCIP
Giải thích chi tiết về linh kiện  3V 128M-BIT SERIAL FLASH MEMORY WITH DUAL/QUAD SPI & QPI
PDF  97 Pages
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W25Q128FV
Publication Release Date: October 01, 2012
- 84 -
Revision D
9.7 AC Electrical Characteristics (cont’d)
DESCRIPTION
SYMBOL
ALT
SPEC
UNIT
MIN
TYP
MAX
/HOLD Active Hold Time relative to CLK
tCHHH
5
ns
/HOLD Not Active Setup Time relative to CLK
tHHCH
5
ns
/HOLD Not Active Hold Time relative to CLK
tCHHL
5
ns
/HOLD to Output Low-Z
tHHQX(2)
tLZ
7
ns
/HOLD to Output High-Z
tHLQZ(2)
tHZ
12
ns
Write Protect Setup Time Before /CS Low
tWHSL(3)
20
ns
Write Protect Hold Time After /CS High
tSHWL(3)
100
ns
/CS High to Power-down Mode
tDP(2)
3
µs
/CS High to Standby Mode without ID Read
tRES1(2)
3
µs
/CS High to Standby Mode with ID Read
tRES2(2)
1.8
µs
/CS High to next Instruction after Suspend
tSUS(2)
20
µs
/CS High to next Instruction after Reset
tRST(2)
30
µs
/RESET pin Low period to reset the device
tRESET(2)
1
(5)
µs
Write Status Register Time
tW
10
15
ms
Byte Program Time (First Byte) (4)
tBP1
30
50
µs
Additional Byte Program Time (After First Byte) (4)
tBP2
2.5
12
µs
Page Program Time
tPP
0.7
3
ms
Sector Erase Time (4KB)
tSE
100
400
ms
Block Erase Time (32KB)
tBE1
120
1,600
ms
Block Erase Time (64KB)
tBE2
150
2,000
ms
Chip Erase Time
tCE
40
200
s
Notes:
1.
Clock high + Clock low must be less than or equal to 1/fC.
2.
Value guaranteed by design and/or characterization, not 100% tested in production.
3.
Only applicable as a constraint for a Write Status Register instruction when SRP[1:0]=(0,1).
4.
For multiple bytes after first byte within a page,
tBPN = tBP1 + tBP2 * N (typical) and tBPN = tBP1 + tBP2 * N (max), where N =
number of bytes programmed.
5.
It is possible to reset the device with shorter tRESET (as short as a few hundred ns), a 1us minimum is recommended to
ensure reliable operation.
6.
Tested on sample basis and specified through design and characterization data. TA = 25° C, VCC = 3.0V, 25% driver
strength.



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