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MPC911 bảng dữ liệu(PDF) 1 Page - Motorola, Inc

tên linh kiện MPC911
Giải thích chi tiết về linh kiện  LOW-VOLTAGE 1:9 DIFFERENTIAL ECL/HSTL TO HSTL CLOCK DRIVER
PDF  4 Pages
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nhà sản xuất  MOTOROLA [Motorola, Inc]
Trang chủ  http://www.freescale.com
Logo MOTOROLA - Motorola, Inc

MPC911 bảng dữ liệu(HTML) 1 Page - Motorola, Inc

  MPC911 Datasheet HTML 1Page - Motorola, Inc MPC911 Datasheet HTML 2Page - Motorola, Inc MPC911 Datasheet HTML 3Page - Motorola, Inc MPC911 Datasheet HTML 4Page - Motorola, Inc  
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
1
REV 1
© Motorola, Inc. 1996
1/96
Low-Voltage 1:9 Differential
ECL/HSTL to HSTL Clock Driver
The MPC9111 is a low skew 1–to–9 differential HSTL compatible
output fanout buffer. The device is functionally equivalent to the
MC100LVE111 device. The device accepts either LVPECL or HSTL
compatible input levels and provides 9 low skew differential HSTL
compatible outputs. The device operates from a single 3.3V VCC supply.
• 800ps Part–to–Part Skew
• 250ps Output–to–Output Skew
• Open Emitter HSTL Compatible Outputs
• Differential Design
• 28–Lead PLCC
• 3.3V VCC
The MPC911 HSTL outputs are not realized in the conventional
manner. To minimize part–to–part and output–to–output skew the HSTL
compatible output levels are generated with an open emitter architecture.
The outputs are pulled down with 50
Ω to ground rather than the typical
50
Ω to VDDQ pullup of a “standard” HSTL output. Because the HSTL
outputs are pulled to ground the MPC911 does not utilize the VDDQ supply
of the HSTL standard. The output levels are derived from VCC, an internal
regulator minimizes the output level variation with VCC variations.
1
56
7
8
9
10
11
25
24
23
22
21
20
19
26
27
28
2
3
4
18
17
16
15
14
13
12
VEE
CLK_Sel
HSTL_CLK
VCC
HSTL_CLK
PECL_CLK
PECL_CLK
Q3
Q3
Q4
VCCO
Q4
Q5
Q5
Pinout: 28-Lead PLCC (Top View)
Q0
Q0
Q1
VCCO Q1
Q2
Q2
Q8
Q7
Q6
Q8
VCCO Q7
Q6
MPC911
LOW-VOLTAGE
1:9 DIFFERENTIAL ECL/HSTL
TO HSTL CLOCK DRIVER
FN SUFFIX
PLASTIC PACKAGE
CASE 776-02
PIN NAMES
Function
Differential HSTL Input
Differential PECL Input
Differential Outputs
Pins
HSTL_CLK, HSTL_CLK
PECL_CLK, PECL_CLK
Q0–Q8, Q0–Q8


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