SPRUG09 datasheet(6/214 Pages) TI

6 / 214 page

TMS320C6474

SPRS552H

– OCTOBER 2008 – REVISED APRIL 2011

www.ti.com

Features

................................................... 1

5.6

Megamodule Resets

................................ 63

1.1

CUN/GUN/ZUN BGA Package (Bottom View)

....... 2

5.7

Megamodule Revision

.............................. 63

1.2

Description

........................................... 3

5.8

C64X+ Megamodule Register Description(s)

....... 64

1.3

C6474 Functional Block Diagram

.................... 5

Device Operating Conditions

....................... 72

6.1

Absolute Maximum Ratings Over Operating Case

Revision History

.............................................. 7

Temperature Range (Unless Otherwise Noted)

.... 72

Device Overview

........................................ 8

6.2

Recommended Operating Conditions

.............. 73

2.1

Device Characteristics

............................... 8

6.3

Electrical Characteristics Over Recommended

2.2

CPU (DSP Core) Description

........................ 9

Ranges of Supply Voltage and Operating Case

2.3

Memory Map Summary

............................. 12

Temperature (Unless Otherwise Noted)

............ 74

2.4

Boot Sequence

..................................... 15

Peripheral Information and Electrical

Specifications

.......................................... 75

2.5

Pin Assignments

.................................... 17

7.1

Parameter Information

.............................. 75

2.6

Signal Groups Description

.......................... 21

7.2

Recommended Clock and Control Signal Transition

2.7

Terminal Functions

................................. 26

Behavior

............................................ 76

2.8

Development and Device Support

.................. 41

7.3

Power Supplies

..................................... 76

2.9

Documentation Support

............................ 42

7.4

Peripheral IDs (PIDs)

............................... 79

2.10

Community Resources

............................. 44

7.5

Enhanced Direct Memory Access (EDMA3)

Device Configuration

................................. 45

Controller

........................................... 80

7.6

Interrupts

.......................................... 104

3.1

Device Configuration at Device Reset

.............. 45

7.7

Reset Controller

................................... 112

3.2

Peripheral Selection After Device Reset

........... 45

7.8

PLL1 and PLL1 Controller

......................... 117

3.3

Device State Control Registers

..................... 46

7.9

PLL2 and PLL2 Controller

......................... 130

3.4

Device Status Register Descriptions

............... 47

7.10

DDR2 Memory Controller

......................... 132

3.5

Inter-DSP Interrupt Registers (IPCGR0-IPCGR2

7.11

I2C Peripheral

..................................... 135

and IPCAR0-IPCAR2)

.............................. 49

7.12

Multichannel Buffered Serial Port (McBSP)

....... 140

3.6

JTAG ID (JTAGID) Register Description

........... 50

7.13

Ethernet MAC (EMAC)

............................ 149

3.7

Debugging Considerations

......................... 50

7.14

Management Data Input/Output (MDIO)

.......... 157

System Interconnect

.................................. 51

7.15

Timers

............................................. 159

4.1

Internal Buses, Switch Fabrics, and

7.16

Enhanced Viterbi-Decoder Coprocessor (VCP2)

Bridges/Gaskets

.................................... 51

..................................................... 168

7.17

Enhanced Turbo Decoder Coprocessor (TCP2)

4.2

Data Switch Fabric Connections

................... 52

..................................................... 170

4.3

Configuration Switch Fabric

........................ 55

7.18

Serial RapidIO (SRIO) Port

....................... 172

4.4

Priority Allocation

................................... 57

7.19

General Purpose Input/Output (GPIO)

............ 184

C64x+ Megamodule

................................... 58

7.20

Emulation Features and Capability

............... 185

5.1

Megamodule Diagram

.............................. 58

7.21

Semaphore

........................................ 189

5.2

Memory Architecture

............................... 59

7.22

Antenna Interface Subsystem

..................... 192

7.23

Frame Synchronization

............................ 204

5.3

Memory Protection

................................. 61

Mechanical Data

...................................... 208

5.4

Bandwidth Management

............................ 62

8.1

Thermal Data

...................................... 208

5.5

Power-Down Control

............................... 63

8.2

Packaging Information

............................ 208

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