OR3C80 datasheet(48/210 Pages) AGERE

48 / 210 page

Lucent Technologies Inc.

Data Sheet

June 1999

ORCA Series 3C and 3T FPGAs

High-Level Routing Resources (continued)

Figure 29 shows the connections from the interquad

routing to the inter-PLC routing for a block of the hori-

zontal interquad. The vertical interquad has similar

connections. The connections shown in Figure 29 are

made with PLCs located above and below the routing

shown in the figure. The interquad routing segments,

prefixed IH for interquad horizontal, are in ten groups of

five lines. Any one line from each group can be routed

to one of the xH segments from the top of the device

(left for vertical interquad), one of the xH segments

from the bottom of the device (right for vertical inter-

quad), and one of the x5 segments crossing the inter-

quad.

Figure 28 shows four fast middle clock (fast clock) sig-

nals with the suffixes T (top), B (bottom), R (right), and

L (left), respectively. Figure 29 also shows the fast

clock R and fast clock L lines; these are dedicated

interquad clock spines. They originate in the CLKCN-

TRL special function blocks in the middle of each edge

of the device, with the name referencing the edge of

origin. For example, fast clock R originates in the

CLKCNTRL block on the right edge of a device. Fast

clock spines traverse the entire PLC array but do not

connect to the PICs on the edge of the device opposite

to the source. Each fast clock line connects to two of

the xL lines in each PLC that run orthogonally to the

fast clock. These connections allow the fast clock lines

to generate a clock tree that can reach any PLC in the

device. Fast clocks and other clock resources are dis-

cussed in the Clock Distribution Network section.

Programmable Corner Cell Routing

Programmable Routing

The programmable corner cell (PCC) contains the cir-

cuitry to connect the routing of the two PICs in each

corner of the device. The PIC px1 and px2 segments

and eight PIC switching segments are directly con-

nected together from one PIC to another. The px5 lines

are all broken with CIPs and the PIC pxL and pxH

segments are connected from one block to another

through programmable buffers.

Corner Cell Special Functions

In addition to routing functions, special-purpose func-

tions are located in each FPGA corner. The upper-left

PCC contains connections to the boundary-scan logic

and microprocessor interface. The upper-right PCC

contains connections to the readback logic, connectiv-

ity to the global 3-state signal (TS_ALL), and a pro-

grammable clock manager. The lower-left PCC

contains connections to the internal oscillator and a

programmable clock manager. The lower-right PCC

contains connections to the start-up and global reset

logic. These functions are all more completely

described in the Special Function Blocks section of this

data sheet.

5-5821(F)

Figure 29. hIQ Block Detail

IH 0[4:0]

IH 1[4:0]

IH 2[4:0]

IH 3[4:0]

IH 4[4:0]

FAST C LO C K R

IH 5[4:0]

IH 6[4:0]

IH 7[4:0]

IH 8[4:0]

IH 9[4:0]

FAST C LO C K L

B L[9:0] vxL[9:0] vx5[9:0] vx1[9:0]

S U L[9:0]

vx1[9:0]

vxH [9:0] B L[9:0]

FAST

vck

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