CT2579 datasheet(14/41 Pages) AEROFLEX

14 / 41 page

APPLICATION NOTE #108

Released 9/98

BLOCK TRANSFER LOGIC / DMA TRANSFER TIMES

All reads and writes to the BTL are identical to read / write to the main RAM. The address

locations are the same. The only difference is that the BTL circuitry will intercept those read

/ writes and store them in the buffer instead. The user accesses the same locations as if they

would if they were directly accessing the main RAM.

The block transfer logic may also be configured by writing to certain address locations

providing NENBTL is selected, ie.

0 1 00 02

402h

Disable Read

Disable Write

0 1 00 03

403h

Disable Read

Enable Write

0 1 00 04

404h

Enable Read

Disable Write

0 1 00 05

405h

Enable Read

Enable Write

Reset will enable both Write and Read.

WRITE

The Write BTL Logic basically stores all writes to a particular subaddress in the buffer until

the subsystem has completed the entire subaddress update. When the subsystem has

finished, the BTL will generate a burst DMA from the BTL to main RAM in one contiguous

transfer. This guarantees that the entire subaddress is updated. Until the DMA transfer the

BTL buffer allows the main RAM to be free for updates from the 1553 data bus.

The user must write data to the device in a specific sequence starting with the first word for

transmission in the n-1 location and ending with the last word for transmission in location 00

of the subaddress. The BTL will sense the write to location 00 and initiate the DMA

sequence.

1. Data for one message is written to the 32 word buffer memory at any speed by the

subsystem. The first word for transmission is written first to the n-1 location and the last

word for transmission is written last to the 00 location of the subaddress.

2. The address of the first word is stored in a register / counter within the "block transfer

logic".

3. The last word for transmission is always written to location zero, this will trigger the

transfer of data from the 32 word buffer memory to the main memory. Data is transferred

at the rate of 250 nS per word. A full 32 word transfer will take approximately 8 uS.

4. If the 1553 is quiet the entire message will immediately be transferred in a single burst to

the main memory, the address being generated by the counter within the block transfer

logic. During this transfer the subsystem will be locked out via NACK from any new

updates.

5. If the 1553 DMA transfer to the main RAM becomes active during the burst transfer, the

transfer will complete and then be locked out of any new updates until the 1553 is

complete. However the BTL buffer memory will be accessible to the subsystem at this

time.

6. If the 1553 DMA transfer to the main RAM becomes active before the start of the burst

transfer, the transfer will be locked out (after location zero is written to) until the 1553 is

complete. The sub system will be locked out during this time (main ram being accessed

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