Aeroflex Circuit Technology

26

SCDCT2553 REV B 8/6/99 Plainview NY (516) 694-6700

A02

A01

A00

MEM/REG

D15-D00

IOEN

SELECT

STRBD)

(Internal)

16MHz Clock

RD/WR

READYD

See Note 1

td1

td8

tpw1

CPU DATA

EXTLD

td9

VALID

VALID

tpw6

td5

td2

Figure 29 – CPU Writes to External Register

CPU Writes to External Register

SYMBOL

DESCRIPTION

MIN

MAX

UNITS

td1

READYD low delay (CPU Handshake)

-

150

ns

td2

IOEN high delay (CPU Handshake)

-

20

ns

tpw1

READYD pulse width (CPU Handshake)

50

-

ns

td5

EXTLD low delay

50

-

ns

td8

Register Data/Address set-up time

-

30

ns

td9

Register Data/Address set-up time

-

0

ns

tpw6

EXTLD low pulse width

56

-

ns

tr

READYD to STRBD release

-

1.37

µs

tz

-

1.8

µs

tz

tr

See Note 2

NOTE:

1. STRBD to IOEN (low) delay is two clock cycles. If contention occurs, delay is two clock cycles following release of bus.

2. CPU must release STRBD within 1.5µs of IOEN going active. READYD will go away within one clock cycle maximum.