LTM4613 datasheet(9/28 Pages) LINER

9 / 28 page

LTM8001

8001f

For more information www.linear.com/8001

PIN FUNCTIONS

VIN0 (Bank 1): The VIN0 bank supplies current to the

LTM8001’s internal regulator and to the internal power

switches. This pin must be locally bypassed with an ex-

ternal, low ESR capacitor; see Table 1 for recommended

values.

GND (Bank 2): Tie these GND pins to a local ground plane

below the LTM8001 and the circuit components. In most

applications, the bulk of the heat flow out of the LTM8001

is through these pads, so the printed circuit design has a

large impact on the thermal performance of the part. See

the PCB Layout and Thermal Considerations sections for

moredetails.Returnthefeedbackdivider(RFB0)tothisnet.

VIN45 (Bank 3): Input to the LDOs connected to VOUT4and

VOUT5.ItmustbelocallybypassedwithalowESRcapacitor.

VOUT0 (Bank 4): Switching Power Converter Output Pins.

Applytheoutputfiltercapacitorandtheoutputloadbetween

these pins and the GND pins. In most cases, an output

capacitancemadeupofacombinationofceramicandelec-

trolytic capacitors yields the optimal volumetric solution.

BIAS45 (Pin A8): This pin is the supply pin for the control

circuitry of the LDOs connected to VOUT4 and VOUT5. For

the LDOs to regulate, this voltage must be more than

1.2V to 1.6V greater than the output voltage (see Dropout

specifications).

BIAS123 (Pin B8): This pin is the supply pin for the

control circuitry of the LDOs connected to VOUT1-VOUT3.

For the LDOs to regulate, this voltage must be more than

1.2V to 1.6V greater than the output voltage (see Dropout

specifications).

SS(PinK4):TheSoft-StartPin.Placeanexternalcapacitor

to ground to limit the regulated current during start-up

conditions.Thesoft-startpinhasan11μAchargingcurrent.

SYNC (Pin K7): Frequency Synchronization Pin. This pin

allows the switching frequency to be synchronized to

an external clock. The RT resistor should be chosen to

operate the internal clock at 20% slower than the SYNC

pulse frequency. This pin should be grounded when not

in use. Do not leave this pin floating. When laying out the

board, avoid noise coupling to or from the SYNC trace.

See the Switching Frequency Synchronization section in

Applications Information.

VREF (Pin K8): Buffered 2V Reference Capable of 0.5mA

Drive.

RUN (Pin L4): The RUN pin acts as an enable pin and

turns on the internal circuitry. The pin does not have any

pull up or pull down, requiring a voltage bias for normal

part operation. The RUN pin is internally clamped, so it

may be pulled up to a voltage source that is higher than

TYPICAL PERFORMANCE CHARACTERISTICS

(TA = 25°C unless otherwise noted. Configured per Table 1, where applicable.)

LDO VBIAS Ripple Rejection

(VOUT4 = 2.5V, VBIAS45 = 4.5V,

VIN45 = 3.5V)

LDO Output Ripple

FREQUENCY (Hz)

100

8001 G38

102

103

104

105

106

ILOAD = 100mA

ILOAD = 1.1A

2µs/DIV

VOUT = 1.2V AT 700mA

COUT1 = 22µF

CSET1 = 1nF

VIN = 12V

VOUT0 = 1.8V LOADED TO

A TOTAL CURRENT OF 5A

100MHz BW

8001 G39

1mV/DIV

LTM4613 bảng dữ liệu(PDF) 9 Page - Linear Technology

LTM4613 bảng dữ liệu(HTML) 9 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

bảng dữ liệu tải về

Link URL