SSM2163

REV. 0

–10–

THEORY OF OPERATION

The SSM2163 is an eight-input, two-output audio mixer and

attenuator. The device provides eight analog inputs, each of

which can be individually attenuated by 0 dB to 63 dB in 1 dB

steps (see the SSM2163 simplified block diagram). The eight

signals can then be mixed into one or both of two analog

outputs. The channel attenuation level and mixer functions

are controlled by digital registers, which are loaded via a

serial interface. A hardware mute input is included to

asynchronously force all inputs into the muted state.

Analog Section

The analog signal path is shown in Figure 20. Each analog input

has a nominal impedance of 10 k

Ω. Each input therefore

appears as a digitally programmable 10 k

Ω potentiometer. The

SSM2163 input impedance remains constant as the attenuation

level changes. Therefore, the sources which drive the SSM2163

do not have to drive complex and variable impedances.

The attenuated analog input is applied to the left and right

channel inputs of the mixer. Each mixer channel consists of an

analog switch and a buffer amplifier. If the channel is selected

(via the appropriate bit in the mixer control register), the analog

switch is turned on. The buffer amplifier is included after the

analog switch so that the gain of each channel will not be

affected by the potentiometer setting or by the on-resistance

(RDS(ON)) of the switch.

Each mixer channel which is ON is then summed into its

respective (Left or Right) mixer summing amplifier. (If both of

the mixer channels are ON, then the attenuated analog input

will be applied to both the Left and Right summing amplifiers.)

The buffered output of the summing amplifier will supply

±500 µA to an external load.

R1

R2

R63

AGND

1 OF 63

DECODER

ATTENTION VALUE

FROM DATA REGISTER

NOTE: ONLY ONE OF EIGHT CHANNELS

SHOWN FOR CLARITY

ATTENUATOR

AGND

AGND

CH1L

SELECT

CH1R

SELECT

MIXER

SWITCH

MIXER

BUFFER AMP

TO INPUTS

K = 1

K = 1

OUTPUT

BUFFER

SUMMING

AMPLIFIER

Figure 20. SSM2163 Analog Signal Path

Digital Interface

The digital interface consists of two banks of 8 data registers

with a serial interface (Figure 21). One register bank holds the

left/right mixer control bits, while the other register bank holds

the 6-bit attenuator value.

TO ATTENUATOR

SWITCHES

TO MIXER

SWITCHES

ATTENUATOR

LEVEL

DATA

LATCHES

(6 BITS)

LEFT/RIGHT

CHANNEL

CONTROL

LATCHES

(2 BITS)

RESET

MUTE

INPUT

DATA

CLOCK

INPUT SHIFT REGISTER

SERIAL DATA

OUTPUT

LOAD

CLK

CLK

DATA IN

CLK

WRITE

Figure 21. SSM2163 Serial Data Interface Block Diagram

To access the SSM2163, the host controller (typically a micro-

computer) writes a value to the serial shift register which selects

the appropriate input channel register for subsequent attenuator-

load operations. This write operation also controls the left and

right mixer switches. The next write operation then loads the

6-bit attenuator level into the appropriate register. If a series of

values are going to be written to the same address, for instance

when fading a channel, then only one write operation to the

address register is required.

Serial Data Control Inputs

The SSM2163 provides a simple 3- or 4-wire serial interface

(Figures 22 and 23). Data is input on the DATA IN pin, while

CLK is the serial clock. Data can be shifted into the SSM2163

clock rates up to 1 MHz.

The shift register clock, CLK, is enabled when the WRITE

input is low. The WRITE pin can therefore be used as a chip

select input. However, the shift register contents are not

transferred to the register banks until the rising edge of LOAD.

In most cases, WRITE and LOAD will be tied together, forming

a traditional 3-wire serial interface. See the Microcomputer

Interfaces section of this data sheet for more information.

To enable a data transfer, the WRITE and LOAD inputs are

driven low. The 8-bit serial data, formatted MSB first, is input

on the DATA IN input and clocked into the shift register on the

rising edge of CLK. The data is latched on the rising edge of

WRITE and LOAD. If the data is an address, then the mixer

control is updated. If the data is an attenuator value the rising

edge of WRITE and LOAD will update the appropriate

attenuator value.

MUTE Input

The MUTE pin provides a hardware input to force all the

SSM2163 channels into the muted state. The MUTE input is

active HIGH. Most

µC I/O pins are in a high impedance state or

configured as inputs at power-up, so the SSM2163 will

automatically be muted at power-up. A 10 k

Ω resistor to +5 V is

recommended, to ensure that MUTE is pulled high reliably.

The MUTE input can also be driven from a

µC’s RESET signal

to force a power-on mute.

In addition to power-on, the MUTE input can be used to

asynchronously mute all channels at any time. The mute

function of the SSM2163 does not affect the attenuator values