RT8057 datasheet(10/11 Pages) RICHTEK

10 / 11 page

RT8057

DS8057-03

November 2011

www.richtek.com

Thermal Considerations

For continuous operation, do not exceed absolute

maximum junction temperature. The maximum power

dissipation depends on the thermal resistance of the IC

package, PCB layout, rate of surrounding airflow, and

difference between junction and ambient temperature. The

maximum power dissipation can be calculated by the

following formula :

PD(MAX) = (TJ(MAX)

− TA) / θJA

where TJ(MAX) is the maximum junction temperature, TA is

the ambient temperature, and

θJA is the junction to ambient

thermal resistance.

For recommended operating condition specifications of

the RT8057, the maximum junction temperature is 125

°C

and TA is the ambient temperature. The junction to ambient

thermal resistance,

θJA, is layout dependent. For

WDFN-6SL 2x2 packages, the thermal resistance,

θJA, is

165

°C/W on a standard JEDEC 51-3 single-layer thermal

test board. The maximum power dissipation at TA = 25

°C

can be calculated by the following formula :

PD(MAX) = (125

°C − 25°C) / (165°C/W) = 0.606W for

WDFN-6SL 2x2 package

The maximum power dissipation depends on the operating

ambient temperature for fixed TJ(MAX) and thermal

resistance,

θJA. For the RT8057 package, the derating

curve in Figure 2 allows the designer to see the effect of

rising ambient temperature on the maximum power

dissipation.

Figure 2. Derating Curve for the RT8057 Package

Layout Considerations

Follow the PCB layout guidelines for optimal performance

of the RT8057.

}

Connect the terminal of the input capacitor(s), CIN, as

close as possible to the VIN pin. This capacitor provides

the AC current into the internal power MOSFETs.

}

LX node experiences high frequency voltage swing and

should be kept within a small area. Keep all sensitive

small-signal nodes away from the LX node to prevent

stray capacitive noise pick up.

}

Flood all unused areas on all layers with copper. Flooding

with copper will reduce the temperature rise of power

components. Connect the copper areas to any DC net

(VIN, VOUT, GND, or any other DC rail in the system).

}

Connect the FB pin directly to the feedback resistors.

The resistive voltage divider must be connected between

VOUT and GND.

Figure 3. PCB Layout Guide

GND

VIN

VOUT

COUT

CIN

Input capacitor must

be placed as close to

the IC as possible.

LX should be connected to inductor by

wide and short trace. Keep sensitive

components away from this trace.

0.00

0.05

0.10

0.15

0.20

0.25

0.30

0.35

0.40

0.45

0.50

0.55

0.60

0.65

100

125

Ambient Temperature (

°C)

Single-Layer PCB

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